From patchwork Tue Feb 7 13:16:51 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Robert_Deli=C3=ABn?= X-Patchwork-Id: 139926 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 707EA1007D3 for ; Wed, 8 Feb 2012 00:34:39 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9DE9B28119; Tue, 7 Feb 2012 14:34:19 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 2aPEX92iv99l; Tue, 7 Feb 2012 14:34:19 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2BD6F280E6; Tue, 7 Feb 2012 14:33:57 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3EF6A280D2 for ; Tue, 7 Feb 2012 14:33:54 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id z0t3MkRfQD04 for ; Tue, 7 Feb 2012 14:33:53 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from aglcosbs04.cos.agilent.com (aglcosbs04.cos.agilent.com [192.25.218.38]) by theia.denx.de (Postfix) with ESMTPS id E4FE0280DB for ; Tue, 7 Feb 2012 14:33:52 +0100 (CET) Received: from localhost.localdomain (unknown [156.141.90.141]) by aglcosbs04.cos.agilent.com (Postfix) with ESMTP id B9F446A375; Tue, 7 Feb 2012 13:33:50 +0000 (GMT) From: robert@delien.nl To: u-boot@lists.denx.de Date: Tue, 7 Feb 2012 14:16:51 +0100 Message-Id: <1328620611-24108-5-git-send-email-robert@delien.nl> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1328620611-24108-1-git-send-email-robert@delien.nl> References: <1328620611-24108-1-git-send-email-robert@delien.nl> X-Virus-Scanned: clamav-milter 0.95.3 at aglcosbs04.cos.agilent.com X-Virus-Status: Clean Cc: Robert Delien Subject: [U-Boot] [PATCH 4/4 v4] Preventing needless switching on and off PLL bypass mode, allowing allow single-stepping through the SPL X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Robert Delien This patch prevents the needless switching on and off of PLL bypass mode. With this patch in place, single-stepping through the SPL is now possible. Signed-off-by: Robert Delien --- arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c | 4 ---- arch/arm/cpu/arm926ejs/mx28/spl_power_init.c | 24 ------------------------ 2 files changed, 0 insertions(+), 28 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c index f2fab7c..cf4361c 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c @@ -121,10 +121,6 @@ void mx28_mem_setup_cpu_and_hbus(void) writeb(19 & CLKCTRL_FRAC_FRAC_MASK, (uint8_t *)&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]); - /* Set CPU bypass */ - writel(CLKCTRL_CLKSEQ_BYPASS_CPU, - &clkctrl_regs->hw_clkctrl_clkseq_set); - /* HBUS = 151MHz */ writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set); writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK, diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c index 380b120..5e21a1e 100644 --- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c @@ -30,28 +30,6 @@ #include "mx28_init.h" -void mx28_power_clock2xtal(void) -{ - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - - /* Set XTAL as CPU reference clock */ - writel(CLKCTRL_CLKSEQ_BYPASS_CPU, - &clkctrl_regs->hw_clkctrl_clkseq_set); -} - -void mx28_power_clock2pll(void) -{ - struct mx28_clkctrl_regs *clkctrl_regs = - (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE; - - writel(CLKCTRL_PLL0CTRL0_POWER, - &clkctrl_regs->hw_clkctrl_pll0ctrl0_set); - early_delay(100); - writel(CLKCTRL_CLKSEQ_BYPASS_CPU, - &clkctrl_regs->hw_clkctrl_clkseq_clr); -} - void mx28_power_clear_auto_restart(void) { struct mx28_rtc_regs *rtc_regs = @@ -606,7 +584,6 @@ void mx28_power_configure_power_source(void) mx28_src_power_init(); mx28_5v_boot(); - mx28_power_clock2pll(); mx28_init_batt_bo(); mx28_switch_vddd_to_dcdc_source(); @@ -880,7 +857,6 @@ void mx28_power_init(void) struct mx28_power_regs *power_regs = (struct mx28_power_regs *)MXS_POWER_BASE; - mx28_power_clock2xtal(); mx28_power_clear_auto_restart(); mx28_power_set_linreg(); mx28_power_setup_5v_detect();