Patchwork [v2] cpu-exec.c: Correct comment about this file and indentation cleanup

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Submitter 陳韋任
Date Feb. 6, 2012, 6:02 a.m.
Message ID <20120206060255.GA55374@cs.nctu.edu.tw>
Download mbox | patch
Permalink /patch/139685/
State New
Headers show

Comments

陳韋任 - Feb. 6, 2012, 6:02 a.m.
Each target use #define marco (in target-xxx/cpu.h) to rename cpu_exec
(cpu-exec.c) to cpu_xxx_exec, then defines its own cpu_loop which calls
cpu_xxx_exec. So basically, cpu-exec.c is not i386 (only) emulator main
execution loop. This patch correctes the comment of this file and does
indentation cleanup.

Signed-off-by: Chen Wei-Ren (陳韋任) <chenwj@iis.sinica.edu.tw>
---
v1 -> v2:

 Didn't notice tab in previous patch, please use this patch instead. 
 Sorry about that.

 cpu-exec.c |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)
Stefan Hajnoczi - Feb. 9, 2012, 8:38 a.m.
On Mon, Feb 06, 2012 at 02:02:55PM +0800, 陳韋任 wrote:
>   Each target use #define marco (in target-xxx/cpu.h) to rename cpu_exec
> (cpu-exec.c) to cpu_xxx_exec, then defines its own cpu_loop which calls
> cpu_xxx_exec. So basically, cpu-exec.c is not i386 (only) emulator main
> execution loop. This patch correctes the comment of this file and does
> indentation cleanup.
> 
> Signed-off-by: Chen Wei-Ren (陳韋任) <chenwj@iis.sinica.edu.tw>
> ---
> v1 -> v2:
> 
>  Didn't notice tab in previous patch, please use this patch instead. 
>  Sorry about that.
> 
>  cpu-exec.c |   10 +++++-----
>  1 files changed, 5 insertions(+), 5 deletions(-)

Thanks, applied to the trivial patches tree:
https://github.com/stefanha/qemu/commits/trivial-patches

Stefan

Patch

diff --git a/cpu-exec.c b/cpu-exec.c
index a9fa608..2c2d24e 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -1,5 +1,5 @@ 
 /*
- *  i386 emulator main execution loop
+ *  emulator main execution loop
  *
  *  Copyright (c) 2003-2005 Fabrice Bellard
  *
@@ -304,7 +304,7 @@  int cpu_exec(CPUState *env)
                             env->hflags2 |= HF2_NMI_MASK;
                             do_interrupt_x86_hardirq(env, EXCP02_NMI, 1);
                             next_tb = 0;
-			} else if (interrupt_request & CPU_INTERRUPT_MCE) {
+                        } else if (interrupt_request & CPU_INTERRUPT_MCE) {
                             env->interrupt_request &= ~CPU_INTERRUPT_MCE;
                             do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0);
                             next_tb = 0;
@@ -390,7 +390,7 @@  int cpu_exec(CPUState *env)
                                 next_tb = 0;
                             }
                         }
-		    }
+                    }
 #elif defined(TARGET_ARM)
                     if (interrupt_request & CPU_INTERRUPT_FIQ
                         && !(env->uncached_cpsr & CPSR_F)) {
@@ -429,7 +429,7 @@  int cpu_exec(CPUState *env)
                     {
                         int idx = -1;
                         /* ??? This hard-codes the OSF/1 interrupt levels.  */
-		        switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) {
+                        switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) {
                         case 0 ... 3:
                             if (interrupt_request & CPU_INTERRUPT_HARD) {
                                 idx = EXCP_DEV_INTERRUPT;
@@ -562,7 +562,7 @@  int cpu_exec(CPUState *env)
                 barrier();
                 if (likely(!env->exit_request)) {
                     tc_ptr = tb->tc_ptr;
-                /* execute the generated code */
+                    /* execute the generated code */
                     next_tb = tcg_qemu_tb_exec(env, tc_ptr);
                     if ((next_tb & 3) == 2) {
                         /* Instruction counter expired.  */