From patchwork Fri Feb 3 17:08:19 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 139428 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id B3BDE1048BD for ; Sat, 4 Feb 2012 04:09:23 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 53BA4280CE; Fri, 3 Feb 2012 18:09:22 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ATAhGM3UrYHP; Fri, 3 Feb 2012 18:09:22 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 566E8280D8; Fri, 3 Feb 2012 18:09:20 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CB01A280CE for ; Fri, 3 Feb 2012 18:09:17 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id w2L7fnwUWZSV for ; Fri, 3 Feb 2012 18:09:17 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ee0-f74.google.com (mail-ee0-f74.google.com [74.125.83.74]) by theia.denx.de (Postfix) with ESMTPS id 383DA280B7 for ; Fri, 3 Feb 2012 18:09:15 +0100 (CET) Received: by eekb15 with SMTP id b15so121184eek.3 for ; Fri, 03 Feb 2012 09:09:14 -0800 (PST) Received: by 10.14.29.144 with SMTP id i16mr1642246eea.4.1328288954229; Fri, 03 Feb 2012 09:09:14 -0800 (PST) Received: by 10.14.29.144 with SMTP id i16mr1642212eea.4.1328288954087; Fri, 03 Feb 2012 09:09:14 -0800 (PST) Received: from hpza9.eem.corp.google.com ([74.125.121.33]) by gmr-mx.google.com with ESMTPS id u2si4524642eeb.2.2012.02.03.09.09.14 (version=TLSv1/SSLv3 cipher=AES128-SHA); Fri, 03 Feb 2012 09:09:14 -0800 (PST) Received: from sglass.mtv.corp.google.com (sglass.mtv.corp.google.com [172.22.72.144]) by hpza9.eem.corp.google.com (Postfix) with ESMTP id DE9325C0050; Fri, 3 Feb 2012 09:09:13 -0800 (PST) Received: by sglass.mtv.corp.google.com (Postfix, from userid 121222) id 38079140B15; Fri, 3 Feb 2012 09:09:13 -0800 (PST) From: Simon Glass To: U-Boot Mailing List Date: Fri, 3 Feb 2012 09:08:19 -0800 Message-Id: <1328288907-16725-11-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 1.7.7.3 Cc: Jerry Van Baren , Tom Warren , linux-tegra@vger.kernel.org, Devicetree Discuss Subject: [U-Boot] [PATCH v6 10/18] tegra: usb: fdt: Add additional device tree definitions for USB ports X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de This adds clock references to the USB part of the device tree for U-Boot, and marks USB1 as supporting legacy mode (which we disable in the driver). The USB timing information may vary between boards sometimes, but for now we hard-code it in C. This is because all current T2x boards use the same values, we will deal with T3x later and we first need to agree on the format for this timing information in the fdt and may in fact decide that it has no place there. Signed-off-by: Simon Glass --- Changes in v5: - Add dr_mode property to control host/device/otg mode - Add nvidia,has-legacy-mode property per review comments - Change device tree comment style from // to /* */ Changes in v6: - Remove dr_mode properties from SOC .dtsi file and move to boards arch/arm/dts/tegra20.dtsi | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/arm/dts/tegra20.dtsi b/arch/arm/dts/tegra20.dtsi index ec75747..df1eda4 100644 --- a/arch/arm/dts/tegra20.dtsi +++ b/arch/arm/dts/tegra20.dtsi @@ -176,6 +176,8 @@ reg = <0xc5000000 0x4000>; interrupts = < 52 >; phy_type = "utmi"; + clocks = <&periph_clk 22>; /* PERIPH_ID_USBD */ + nvidia,has-legacy-mode; }; usb@c5004000 { @@ -183,6 +185,7 @@ reg = <0xc5004000 0x4000>; interrupts = < 53 >; phy_type = "ulpi"; + clocks = <&periph_clk 58>; /* PERIPH_ID_USB2 */ }; usb@c5008000 { @@ -190,6 +193,7 @@ reg = <0xc5008000 0x4000>; interrupts = < 129 >; phy_type = "utmi"; + clocks = <&periph_clk 59>; /* PERIPH_ID_USB3 */ }; };