From patchwork Fri Feb 3 02:59:38 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andreas_F=C3=A4rber?= X-Patchwork-Id: 139277 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2B8D2104792 for ; Fri, 3 Feb 2012 14:03:49 +1100 (EST) Received: from localhost ([::1]:44986 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rt9R6-0002GI-Te for incoming@patchwork.ozlabs.org; Thu, 02 Feb 2012 22:03:40 -0500 Received: from eggs.gnu.org ([140.186.70.92]:38715) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rt9Q0-00084v-Hx for qemu-devel@nongnu.org; Thu, 02 Feb 2012 22:02:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rt9Pu-00061v-E9 for qemu-devel@nongnu.org; Thu, 02 Feb 2012 22:02:32 -0500 Received: from cantor2.suse.de ([195.135.220.15]:55626 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rt9Pu-00061Y-4t for qemu-devel@nongnu.org; Thu, 02 Feb 2012 22:02:26 -0500 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 9EDB18FC92; Fri, 3 Feb 2012 04:02:25 +0100 (CET) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= To: qemu-devel@nongnu.org Date: Fri, 3 Feb 2012 03:59:38 +0100 Message-Id: <1328237992-14953-8-git-send-email-afaerber@suse.de> X-Mailer: git-send-email 1.7.7 In-Reply-To: <1328237992-14953-1-git-send-email-afaerber@suse.de> References: <1328237992-14953-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= Subject: [Qemu-devel] [PATCH RFC v3 07/21] target-arm: Overwrite reset handler for ti925t X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The OMAPCP feature allows to switch between TI915T and TI925T via cp15 c15_ticonfig register. Move reset into ti925t-specific callback. Signed-off-by: Andreas Färber Cc: Peter Maydell --- target-arm/cpu.c | 18 ++++++++++++++++++ target-arm/helper.c | 1 - 2 files changed, 18 insertions(+), 1 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index b794ec1..a6dbad3 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -99,6 +99,23 @@ typedef struct ARMCPUInfo { void (*class_init)(ARMCPUClass *klass, const struct ARMCPUInfo *info); } ARMCPUInfo; +static void ti925t_reset(CPU *c) +{ + ARMCPU *cpu = ARM_CPU(c); + CPUARMState *env = &cpu->env; + + arm_cpu_reset(c); + + env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */ +} + +static void ti925t_class_init(ARMCPUClass *klass, const ARMCPUInfo *info) +{ + CPUClass *cpu_class = CPU_CLASS(klass); + + cpu_class->reset = ti925t_reset; +} + static const ARMCPUInfo arm_cpus[] = { { .name = "arm926", @@ -151,6 +168,7 @@ static const ARMCPUInfo arm_cpus[] = { { .name = "ti925t", .id = 0x54029252, + .class_init = ti925t_class_init, }, { .name = "sa1100", diff --git a/target-arm/helper.c b/target-arm/helper.c index c5ba7fd..e877c3f 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -201,7 +201,6 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t id) case ARM_CPUID_TI925T: set_feature(env, ARM_FEATURE_V4T); set_feature(env, ARM_FEATURE_OMAPCP); - env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */ env->cp15.c0_cachetype = 0x5109149; env->cp15.c1_sys = 0x00000070; env->cp15.c15_i_max = 0x000;