From patchwork Thu Feb 2 01:49:28 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 139051 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8B171B6F99 for ; Thu, 2 Feb 2012 13:27:45 +1100 (EST) Received: from localhost ([::1]:50143 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rsloq-0005M2-Lu for incoming@patchwork.ozlabs.org; Wed, 01 Feb 2012 20:50:36 -0500 Received: from eggs.gnu.org ([140.186.70.92]:48508) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rslo9-0004i6-Mf for qemu-devel@nongnu.org; Wed, 01 Feb 2012 20:49:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rslo2-0005SI-N5 for qemu-devel@nongnu.org; Wed, 01 Feb 2012 20:49:53 -0500 Received: from cantor2.suse.de ([195.135.220.15]:49084 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rslo2-0005Rz-EH; Wed, 01 Feb 2012 20:49:46 -0500 Received: from relay1.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 4A0FA90072; Thu, 2 Feb 2012 02:49:45 +0100 (CET) From: Alexander Graf To: qemu-ppc@nongnu.org Date: Thu, 2 Feb 2012 02:49:28 +0100 Message-Id: <1328147384-10387-6-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1328147384-10387-1-git-send-email-agraf@suse.de> References: <1328147384-10387-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: Blue Swirl , qemu-devel Developers , Aurelien Jarno Subject: [Qemu-devel] [PATCH 05/21] PPC: e500: msync is 440 only, e500 has real sync X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The e500 CPUs don't use 440's msync which falls on the same opcode IDs, but instead use the real powerpc sync instruction. This is important, since the invalid mask differs between the two. Signed-off-by: Alexander Graf --- target-ppc/translate.c | 3 +-- target-ppc/translate_init.c | 6 +++--- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 66eae30..18d52a9 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -8579,8 +8579,7 @@ GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE, PPC2_BOOKE206), -GEN_HANDLER_E(msync, 0x1F, 0x16, 0x12, 0x03FFF801, - PPC_BOOKE, PPC2_BOOKE206), +GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE, PPC2_BOOKE206), GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index f5fcd1e..b14a98c 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -4371,7 +4371,7 @@ static void init_proc_e300 (CPUPPCState *env) PPC_WRTEE | PPC_RFDI | \ PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ - PPC_MEM_TLBSYNC | PPC_TLBIVAX) + PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC) #define POWERPC_INSNS2_e500v1 (PPC2_BOOKE206) #define POWERPC_MSRM_e500v1 (0x000000000606FF30ULL) #define POWERPC_MMU_e500v1 (POWERPC_MMU_BOOKE206) @@ -4390,7 +4390,7 @@ static void init_proc_e300 (CPUPPCState *env) PPC_WRTEE | PPC_RFDI | \ PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \ PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ - PPC_MEM_TLBSYNC | PPC_TLBIVAX) + PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC) #define POWERPC_INSNS2_e500v2 (PPC2_BOOKE206) #define POWERPC_MSRM_e500v2 (0x000000000606FF30ULL) #define POWERPC_MMU_e500v2 (POWERPC_MMU_BOOKE206) @@ -4411,7 +4411,7 @@ static void init_proc_e300 (CPUPPCState *env) PPC_FLOAT | PPC_FLOAT_FRES | \ PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \ PPC_FLOAT_STFIWX | PPC_WAIT | \ - PPC_MEM_TLBSYNC | PPC_TLBIVAX) + PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC) #define POWERPC_INSNS2_e500mc (PPC2_BOOKE206) #define POWERPC_MSRM_e500mc (0x000000001402FB36ULL) #define POWERPC_MMU_e500mc (POWERPC_MMU_BOOKE206)