From patchwork Thu Feb 2 01:49:29 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [06/21] PPC: rename msync to msync_4xx Date: Wed, 01 Feb 2012 15:49:29 -0000 From: Alexander Graf X-Patchwork-Id: 139049 Message-Id: <1328147384-10387-7-git-send-email-agraf@suse.de> To: qemu-ppc@nongnu.org Cc: Blue Swirl , qemu-devel Developers , Aurelien Jarno The msync instruction as defined today is only valid on 4xx cores, not on e500 which also supports msync, but treats it the same way as sync. Rename it to reflect that it's 4xx only. Signed-off-by: Alexander Graf --- target-ppc/translate.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 18d52a9..adde65b 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -6172,7 +6172,7 @@ static void gen_mbar(DisasContext *ctx) } /* msync replaces sync on 440 */ -static void gen_msync(DisasContext *ctx) +static void gen_msync_4xx(DisasContext *ctx) { /* interpreted as no-op */ } @@ -8579,7 +8579,7 @@ GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, PPC_BOOKE, PPC2_BOOKE206), -GEN_HANDLER(msync, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), +GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE), GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001, PPC_BOOKE, PPC2_BOOKE206), GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),