From patchwork Tue Jan 31 17:41:28 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Kiszka X-Patchwork-Id: 138831 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 448731007D1 for ; Wed, 1 Feb 2012 05:12:02 +1100 (EST) Received: from localhost ([::1]:41547 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RsHiq-0003Au-RU for incoming@patchwork.ozlabs.org; Tue, 31 Jan 2012 12:42:24 -0500 Received: from eggs.gnu.org ([140.186.70.92]:47095) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RsHiB-0000xK-Dz for qemu-devel@nongnu.org; Tue, 31 Jan 2012 12:41:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RsHi3-00019H-Ta for qemu-devel@nongnu.org; Tue, 31 Jan 2012 12:41:43 -0500 Received: from david.siemens.de ([192.35.17.14]:29473) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RsHi3-00018A-CS for qemu-devel@nongnu.org; Tue, 31 Jan 2012 12:41:35 -0500 Received: from mail1.siemens.de (localhost [127.0.0.1]) by david.siemens.de (8.13.6/8.13.6) with ESMTP id q0VHfWp6016205; Tue, 31 Jan 2012 18:41:32 +0100 Received: from mchn199C.mchp.siemens.de ([139.25.109.49]) by mail1.siemens.de (8.13.6/8.13.6) with ESMTP id q0VHfUpM022802; Tue, 31 Jan 2012 18:41:31 +0100 From: Jan Kiszka To: Anthony Liguori , qemu-devel Date: Tue, 31 Jan 2012 18:41:28 +0100 Message-Id: X-Mailer: git-send-email 1.7.3.4 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) X-Received-From: 192.35.17.14 Cc: Blue Swirl , Marcelo Tosatti , Avi Kivity , kvm Subject: [Qemu-devel] [PATCH v3 5/7] i8254: Rework & fix interaction with HPET in legacy mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org When the HPET enters legacy mode, the IRQ output of the PIT is suppressed and replaced by the HPET timer 0. But the current code to emulate this was broken in many ways. It reset the PIT state after re-enabling, it worked against a stale static PIT structure, and it did not properly saved/restored the IRQ output mask in the PIT vmstate. This patch solves the PIT IRQ control in a different way. On x86, it both redirects the PIT IRQ to the HPET, just like the RTC. But it also keeps the control line from the HPET to the PIT. This allows to disable the PIT QEMU timer when it is not needed. The PIT's view on the control line state is now saved in the same format that qemu-kvm is already using. Note that, in contrast to the suppressed RTC IRQ line, we do not need to save/restore the PIT line state in the HPET. As we trigger a PIT IRQ update via the control line, the line state is reconstructed on mode switch. Signed-off-by: Jan Kiszka --- hw/hpet.c | 38 ++++++++++++++++++++------------------ hw/hpet_emul.h | 3 +++ hw/i8254.c | 46 ++++++++++++++++++++++------------------------ hw/i8254.h | 3 --- hw/pc.c | 15 ++++++++++++--- 5 files changed, 57 insertions(+), 48 deletions(-) diff --git a/hw/hpet.c b/hw/hpet.c index c921ec9..9fbbd47 100644 --- a/hw/hpet.c +++ b/hw/hpet.c @@ -65,6 +65,7 @@ typedef struct HPETState { qemu_irq irqs[HPET_NUM_IRQ_ROUTES]; uint32_t flags; uint8_t rtc_irq_level; + qemu_irq pit_enabled; uint8_t num_timers; HPETTimer timer[HPET_MAX_TIMERS]; @@ -573,12 +574,15 @@ static void hpet_ram_write(void *opaque, target_phys_addr_t addr, hpet_del_timer(&s->timer[i]); } } - /* i8254 and RTC are disabled when HPET is in legacy mode */ + /* i8254 and RTC output pins are disabled + * when HPET is in legacy mode */ if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) { - hpet_pit_disable(); + qemu_set_irq(s->pit_enabled, 0); + qemu_irq_lower(s->irqs[0]); qemu_irq_lower(s->irqs[RTC_ISA_IRQ]); } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) { - hpet_pit_enable(); + qemu_irq_lower(s->irqs[0]); + qemu_set_irq(s->pit_enabled, 1); qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level); } break; @@ -632,7 +636,6 @@ static void hpet_reset(DeviceState *d) { HPETState *s = FROM_SYSBUS(HPETState, sysbus_from_qdev(d)); int i; - static int count = 0; for (i = 0; i < s->num_timers; i++) { HPETTimer *timer = &s->timer[i]; @@ -649,29 +652,27 @@ static void hpet_reset(DeviceState *d) timer->wrap_flag = 0; } + qemu_set_irq(s->pit_enabled, 1); s->hpet_counter = 0ULL; s->hpet_offset = 0ULL; s->config = 0ULL; - if (count > 0) { - /* we don't enable pit when hpet_reset is first called (by hpet_init) - * because hpet is taking over for pit here. On subsequent invocations, - * hpet_reset is called due to system reset. At this point control must - * be returned to pit until SW reenables hpet. - */ - hpet_pit_enable(); - } hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability; hpet_cfg.hpet[s->hpet_id].address = sysbus_from_qdev(d)->mmio[0].addr; - count = 1; } -static void hpet_handle_rtc_irq(void *opaque, int n, int level) +static void hpet_handle_legacy_irq(void *opaque, int n, int level) { HPETState *s = FROM_SYSBUS(HPETState, opaque); - s->rtc_irq_level = level; - if (!hpet_in_legacy_mode(s)) { - qemu_set_irq(s->irqs[RTC_ISA_IRQ], level); + if (n == HPET_LEGACY_PIT_INT) { + if (!hpet_in_legacy_mode(s)) { + qemu_set_irq(s->irqs[0], level); + } + } else { + s->rtc_irq_level = level; + if (!hpet_in_legacy_mode(s)) { + qemu_set_irq(s->irqs[RTC_ISA_IRQ], level); + } } } @@ -714,7 +715,8 @@ static int hpet_init(SysBusDevice *dev) s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT; s->capability |= ((HPET_CLK_PERIOD) << 32); - qdev_init_gpio_in(&dev->qdev, hpet_handle_rtc_irq, 1); + qdev_init_gpio_in(&dev->qdev, hpet_handle_legacy_irq, 2); + qdev_init_gpio_out(&dev->qdev, &s->pit_enabled, 1); /* HPET Area */ memory_region_init_io(&s->iomem, &hpet_ram_ops, s, "hpet", 0x400); diff --git a/hw/hpet_emul.h b/hw/hpet_emul.h index 6128702..757f79f 100644 --- a/hw/hpet_emul.h +++ b/hw/hpet_emul.h @@ -22,6 +22,9 @@ #define HPET_NUM_IRQ_ROUTES 32 +#define HPET_LEGACY_PIT_INT 0 +#define HPET_LEGACY_RTC_INT 1 + #define HPET_CFG_ENABLE 0x001 #define HPET_CFG_LEGACY 0x002 diff --git a/hw/i8254.c b/hw/i8254.c index 326211a..6412277 100644 --- a/hw/i8254.c +++ b/hw/i8254.c @@ -52,6 +52,7 @@ typedef struct PITChannelState { int64_t next_transition_time; QEMUTimer *irq_timer; qemu_irq irq; + uint32_t irq_disabled; } PITChannelState; typedef struct PITState { @@ -61,8 +62,6 @@ typedef struct PITState { PITChannelState channels[3]; } PITState; -static PITState pit_state; - static void pit_irq_timer_update(PITChannelState *s, int64_t current_time); static int pit_get_count(PITChannelState *s) @@ -378,8 +377,9 @@ static void pit_irq_timer_update(PITChannelState *s, int64_t current_time) int64_t expire_time; int irq_level; - if (!s->irq_timer) + if (!s->irq_timer || s->irq_disabled) { return; + } expire_time = pit_get_next_transition_time(s, current_time); irq_level = pit_get_out1(s, current_time); qemu_set_irq(s->irq, irq_level); @@ -450,6 +450,7 @@ static int pit_load_old(QEMUFile *f, void *opaque, int version_id) qemu_get_8s(f, &s->bcd); qemu_get_8s(f, &s->gate); s->count_load_time=qemu_get_be64(f); + s->irq_disabled = 0; if (s->irq_timer) { s->next_transition_time=qemu_get_be64(f); qemu_get_timer(f, s->irq_timer); @@ -460,11 +461,12 @@ static int pit_load_old(QEMUFile *f, void *opaque, int version_id) static const VMStateDescription vmstate_pit = { .name = "i8254", - .version_id = 2, + .version_id = 3, .minimum_version_id = 2, .minimum_version_id_old = 1, .load_state_old = pit_load_old, .fields = (VMStateField []) { + VMSTATE_UINT32_V(channels[0].irq_disabled, PITState, 3), VMSTATE_STRUCT_ARRAY(channels, PITState, 3, 2, vmstate_pit_channel, PITChannelState), VMSTATE_TIMER(channels[0].irq_timer, PITState), VMSTATE_END_OF_LIST() @@ -483,7 +485,7 @@ static void pit_reset(DeviceState *dev) s->gate = (i != 2); s->count_load_time = qemu_get_clock_ns(vm_clock); s->count = 0x10000; - if (i == 0) { + if (i == 0 && !s->irq_disabled) { s->next_transition_time = pit_get_next_transition_time(s, s->count_load_time); qemu_mod_timer(s->irq_timer, s->next_transition_time); @@ -491,26 +493,20 @@ static void pit_reset(DeviceState *dev) } } -/* When HPET is operating in legacy mode, i8254 timer0 is disabled */ -void hpet_pit_disable(void) { - PITChannelState *s; - s = &pit_state.channels[0]; - if (s->irq_timer) - qemu_del_timer(s->irq_timer); -} - -/* When HPET is reset or leaving legacy mode, it must reenable i8254 - * timer 0 - */ - -void hpet_pit_enable(void) +/* When HPET is operating in legacy mode, suppress the ignored timer IRQ, + * reenable it when legacy mode is left again. */ +static void pit_irq_control(void *opaque, int n, int enable) { - PITState *pit = &pit_state; - PITChannelState *s; - s = &pit->channels[0]; - s->mode = 3; - s->gate = 1; - pit_load_count(s, 0); + PITState *pit = opaque; + PITChannelState *s = &pit->channels[0]; + + if (enable) { + s->irq_disabled = 0; + pit_irq_timer_update(s, qemu_get_clock_ns(vm_clock)); + } else { + s->irq_disabled = 1; + qemu_del_timer(s->irq_timer); + } } static const MemoryRegionPortio pit_portio[] = { @@ -536,6 +532,8 @@ static int pit_initfn(ISADevice *dev) memory_region_init_io(&pit->ioports, &pit_ioport_ops, pit, "pit", 4); isa_register_ioport(dev, &pit->ioports, pit->iobase); + qdev_init_gpio_in(&dev->qdev, pit_irq_control, 1); + qdev_set_legacy_instance_id(&dev->qdev, pit->iobase, 2); return 0; diff --git a/hw/i8254.h b/hw/i8254.h index fc64a63..8ad8e07 100644 --- a/hw/i8254.h +++ b/hw/i8254.h @@ -50,7 +50,4 @@ int pit_get_initial_count(ISADevice *dev, int channel); int pit_get_mode(ISADevice *dev, int channel); int pit_get_out(ISADevice *dev, int channel, int64_t current_time); -void hpet_pit_disable(void); -void hpet_pit_enable(void); - #endif /* !HW_I8254_H */ diff --git a/hw/pc.c b/hw/pc.c index 223678d..6fb1de7 100644 --- a/hw/pc.c +++ b/hw/pc.c @@ -1136,6 +1136,9 @@ void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, { int i; DriveInfo *fd[MAX_FD]; + DeviceState *hpet = NULL; + int pit_isa_irq = 0; + qemu_irq pit_alt_irq = NULL; qemu_irq rtc_irq = NULL; qemu_irq *a20_line; ISADevice *i8042, *port92, *vmmouse, *pit; @@ -1146,20 +1149,26 @@ void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); if (!no_hpet) { - DeviceState *hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL); + hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL); if (hpet) { for (i = 0; i < GSI_NUM_PINS; i++) { sysbus_connect_irq(sysbus_from_qdev(hpet), i, gsi[i]); } - rtc_irq = qdev_get_gpio_in(hpet, 0); + pit_isa_irq = -1; + pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT); + rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT); } } *rtc_state = rtc_init(isa_bus, 2000, rtc_irq); qemu_register_boot_set(pc_boot_set, *rtc_state); - pit = pit_init(isa_bus, 0x40, 0, NULL); + pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq); + if (hpet) { + /* connect PIT to output control line of the HPET */ + qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(&pit->qdev, 0)); + } pcspk_init(pit); for(i = 0; i < MAX_SERIAL_PORTS; i++) {