From patchwork Tue Jan 31 14:13:29 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 138787 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (unknown [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B99E1B71AA for ; Wed, 1 Feb 2012 01:16:14 +1100 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1RsESl-0005Yv-UX; Tue, 31 Jan 2012 14:13:36 +0000 Received: from mail-wi0-f177.google.com ([209.85.212.177]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1RsESh-0005YT-QE for linux-arm-kernel@lists.infradead.org; Tue, 31 Jan 2012 14:13:32 +0000 Received: by wico1 with SMTP id o1so5108228wic.36 for ; Tue, 31 Jan 2012 06:13:30 -0800 (PST) MIME-Version: 1.0 Received: by 10.180.92.71 with SMTP id ck7mr44062532wib.3.1328019210088; Tue, 31 Jan 2012 06:13:30 -0800 (PST) Received: by 10.216.30.213 with HTTP; Tue, 31 Jan 2012 06:13:29 -0800 (PST) In-Reply-To: <1327944699-29882-2-git-send-email-robherring2@gmail.com> References: <1327944699-29882-1-git-send-email-robherring2@gmail.com> <1327944699-29882-2-git-send-email-robherring2@gmail.com> Date: Tue, 31 Jan 2012 22:13:29 +0800 Message-ID: Subject: Re: [PATCH v3 1/2] irq: add irq_domain support to generic-chip From: Shawn Guo To: Rob Herring X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.212.177 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: b-cousson@ti.com, linux-kernel@vger.kernel.org, Rob Herring , Grant Likely , Thomas Gleixner , linux-arm-kernel@lists.infradead.org X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org On Mon, Jan 30, 2012 at 11:31:38AM -0600, Rob Herring wrote: ... > +#ifdef CONFIG_IRQ_DOMAIN > +static int irq_gc_irq_domain_match(struct irq_domain *d, struct device_node *np) > +{ > + struct irq_chip_generic *gc; > + > + if (d->of_node != NULL && d->of_node == np) { > + list_for_each_entry(gc, &gc_list, list) { > + if ((gc == d->host_data) && (d == gc->domain)) > + return 1; > + } > + } IIRC, we talked about this a little bit, but I'm still unsure how this works for imx5 tzic case, where we have the same one tzic device_node for 4 irqdomains representing 128 irq lines. It seems to me the match function here will always find the first irqdomain of the 4 for any of those 128 tzic irqs. The following is my code change against your branch for testing. Am I missing anything? 8<--- --->8 > + return 0; > +} > + ... > +void irq_setup_generic_chip_domain(struct irq_chip_generic *gc, > + struct device_node *node, u32 msk, > + enum irq_gc_flags flags, unsigned int clr, > + unsigned int set) > +{ > + struct irq_chip_type *ct = gc->chip_types; > + > + if (!node) { > + irq_setup_generic_chip(gc, msk, flags, clr, set); > + return; > + } > + > + raw_spin_lock(&gc_lock); > + list_add_tail(&gc->list, &gc_list); > + raw_spin_unlock(&gc_lock); > + > + /* Init mask cache ? */ > + if (flags & IRQ_GC_INIT_MASK_CACHE) > + gc->mask_cache = irq_reg_readl(gc->reg_base + ct->regs.mask); > + > + gc->flags = flags; > + gc->irq_clr = clr; > + gc->irq_set = set; > + > + /* Users of domains should not use irq_base */ > + if ((int)gc->irq_base > 0) > + gc->domain = irq_domain_add_legacy(node, fls(msk), > + gc->irq_base, 0, > + &irq_gc_irq_domain_ops, gc); > + else { > + gc->irq_base = 0; > + gc->domain = irq_domain_add_linear(node, fls(msk), > + &irq_gc_irq_domain_ops, gc); > + } We have 4 generic_chips for tzic with irq_base as 0, 32, 64, 96. In this case, we end up with having the first domain as the linear, and the other 3 as the legacy? > +} > +EXPORT_SYMBOL_GPL(irq_setup_generic_chip_domain); > +#endif diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c index e1b5edf..45abf11 100644 --- a/arch/arm/mach-imx/imx51-dt.c +++ b/arch/arm/mach-imx/imx51-dt.c @@ -44,13 +44,6 @@ static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = { { /* sentinel */ } }; -static int __init imx51_tzic_add_irq_domain(struct device_node *np, - struct device_node *interrupt_parent) -{ - irq_domain_add_legacy(np, 32, 0, 0, &irq_domain_simple_ops, NULL); - return 0; -} - static int __init imx51_gpio_add_irq_domain(struct device_node *np, struct device_node *interrupt_parent) { @@ -63,7 +56,6 @@ static int __init imx51_gpio_add_irq_domain(struct device_node *np, } static const struct of_device_id imx51_irq_match[] __initconst = { - { .compatible = "fsl,imx51-tzic", .data = imx51_tzic_add_irq_domain, }, { .compatible = "fsl,imx51-gpio", .data = imx51_gpio_add_irq_domain, }, { /* sentinel */ } }; diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c index 98308ec..ffb615d 100644 --- a/arch/arm/plat-mxc/tzic.c +++ b/arch/arm/plat-mxc/tzic.c @@ -122,7 +122,9 @@ static __init void tzic_init_gc(unsigned int irq_start) ct->regs.disable = TZIC_ENCLEAR0(idx); ct->regs.enable = TZIC_ENSET0(idx); - irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); + irq_setup_generic_chip_domain(gc, + of_find_compatible_node(NULL, NULL, "fsl,tzic"), + IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); } asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)