From patchwork Mon Jan 30 12:41:28 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eric Botcazou X-Patchwork-Id: 138567 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id BD146B6EF1 for ; Mon, 30 Jan 2012 23:45:25 +1100 (EST) Comment: DKIM? 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See http://antispam.yahoo.com/domainkeys DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=gcc.gnu.org; h=Received:Received:X-SWARE-Spam-Status:X-Spam-Check-By:Received:Received:Received:Received:From:To:Subject:Date:User-Agent:MIME-Version:Message-Id:Content-Type:Mailing-List:Precedence:List-Id:List-Unsubscribe:List-Archive:List-Post:List-Help:Sender:Delivered-To; b=hfjE3SfZb/pKcsnmaeR8cbRrjbPUElGaPFNHHkGeo5TDH7DPiiRN4hBU9S2IW8 c8rm6uT4hH9/v1mpcyUegcTa1S84zlVoPgdrAP4XpKHBLPsnh0U3P0uk8E/AYXYR v58YxDc28tul5LIBq1iDLG7lzPMk2PZFXjMiSmLJ4ycIM=; Received: (qmail 5339 invoked by alias); 30 Jan 2012 12:45:10 -0000 Received: (qmail 5236 invoked by uid 22791); 30 Jan 2012 12:45:08 -0000 X-SWARE-Spam-Status: No, hits=-1.9 required=5.0 tests=AWL,BAYES_00 X-Spam-Check-By: sourceware.org Received: from mel.act-europe.fr (HELO mel.act-europe.fr) (194.98.77.210) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 30 Jan 2012 12:44:51 +0000 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id 074F32900B2 for ; Mon, 30 Jan 2012 13:44:51 +0100 (CET) Received: from mel.act-europe.fr ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id b9FHJl38L4UD for ; Mon, 30 Jan 2012 13:44:50 +0100 (CET) Received: from [192.168.1.2] (bon31-6-88-161-99-133.fbx.proxad.net [88.161.99.133]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mel.act-europe.fr (Postfix) with ESMTP id C1505CB3BBB for ; Mon, 30 Jan 2012 13:44:50 +0100 (CET) From: Eric Botcazou To: gcc-patches@gcc.gnu.org Subject: [SPARC] Fix PR target/51920 Date: Mon, 30 Jan 2012 13:41:28 +0100 User-Agent: KMail/1.9.9 MIME-Version: 1.0 Message-Id: <201201301341.29055.ebotcazou@adacore.com> Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org I think it's the long-standing issue with word-mode paradoxical subregs of FP regs in 64-bit mode, which is present on both PA and SPARC. We don't have any real solution as of this writing, only kludges, so the attached patch makes it so that vector_init_fpmerge doesn't create pseudos with long live ranges, to lower the pressure on the register allocator. Tested on SPARC/Solaris, applied on the mainline. 2012-01-30 Eric Botcazou PR target/51920 * config/sparc/sparc.c (vector_init_fpmerge): Remove INNER_MODE parameter and use short-lived pseudos. (vector_init_faligndata): Remove INNER_MODE parameter and use loop. (sparc_expand_vector_init): Const-ify local variables and adjust calls to above functions. Index: config/sparc/sparc.c =================================================================== --- config/sparc/sparc.c (revision 183640) +++ config/sparc/sparc.c (working copy) @@ -11485,49 +11485,47 @@ vector_init_bshuffle (rtx target, rtx el emit_insn (final_insn); } +/* Subroutine of sparc_expand_vector_init. Emit code to initialize + all fields of TARGET to ELT in V8QI by means of VIS FPMERGE insn. */ + static void -vector_init_fpmerge (rtx target, rtx elt, enum machine_mode inner_mode) +vector_init_fpmerge (rtx target, rtx elt) { - rtx t1, t2, t3, t3_low; + rtx t1, t2, t2_low, t3, t3_low; t1 = gen_reg_rtx (V4QImode); - elt = convert_modes (SImode, inner_mode, elt, true); + elt = convert_modes (SImode, QImode, elt, true); emit_move_insn (gen_lowpart (SImode, t1), elt); - t2 = gen_reg_rtx (V4QImode); - emit_move_insn (t2, t1); + t2 = gen_reg_rtx (V8QImode); + t2_low = gen_lowpart (V4QImode, t2); + emit_insn (gen_fpmerge_vis (t2, t1, t1)); t3 = gen_reg_rtx (V8QImode); t3_low = gen_lowpart (V4QImode, t3); + emit_insn (gen_fpmerge_vis (t3, t2_low, t2_low)); - emit_insn (gen_fpmerge_vis (t3, t1, t2)); - emit_move_insn (t1, t3_low); - emit_move_insn (t2, t3_low); - - emit_insn (gen_fpmerge_vis (t3, t1, t2)); - emit_move_insn (t1, t3_low); - emit_move_insn (t2, t3_low); - - emit_insn (gen_fpmerge_vis (gen_lowpart (V8QImode, target), t1, t2)); + emit_insn (gen_fpmerge_vis (target, t3_low, t3_low)); } +/* Subroutine of sparc_expand_vector_init. Emit code to initialize + all fields of TARGET to ELT in V4HI by means of VIS FALIGNDATA insn. */ + static void -vector_init_faligndata (rtx target, rtx elt, enum machine_mode inner_mode) +vector_init_faligndata (rtx target, rtx elt) { rtx t1 = gen_reg_rtx (V4HImode); + int i; - elt = convert_modes (SImode, inner_mode, elt, true); - + elt = convert_modes (SImode, HImode, elt, true); emit_move_insn (gen_lowpart (SImode, t1), elt); emit_insn (gen_alignaddrsi_vis (gen_reg_rtx (SImode), force_reg (SImode, GEN_INT (6)), - CONST0_RTX (SImode))); + const0_rtx)); - emit_insn (gen_faligndatav4hi_vis (target, t1, target)); - emit_insn (gen_faligndatav4hi_vis (target, t1, target)); - emit_insn (gen_faligndatav4hi_vis (target, t1, target)); - emit_insn (gen_faligndatav4hi_vis (target, t1, target)); + for (i = 0; i < 4; i++) + emit_insn (gen_faligndatav4hi_vis (target, t1, target)); } /* Emit code to initialize TARGET to values for individual fields VALS. */ @@ -11535,9 +11533,9 @@ vector_init_faligndata (rtx target, rtx void sparc_expand_vector_init (rtx target, rtx vals) { - enum machine_mode mode = GET_MODE (target); - enum machine_mode inner_mode = GET_MODE_INNER (mode); - int n_elts = GET_MODE_NUNITS (mode); + const enum machine_mode mode = GET_MODE (target); + const enum machine_mode inner_mode = GET_MODE_INNER (mode); + const int n_elts = GET_MODE_NUNITS (mode); int i, n_var = 0; bool all_same; rtx mem; @@ -11593,12 +11591,12 @@ sparc_expand_vector_init (rtx target, rt } if (mode == V8QImode) { - vector_init_fpmerge (target, XVECEXP (vals, 0, 0), inner_mode); + vector_init_fpmerge (target, XVECEXP (vals, 0, 0)); return; } if (mode == V4HImode) { - vector_init_faligndata (target, XVECEXP (vals, 0, 0), inner_mode); + vector_init_faligndata (target, XVECEXP (vals, 0, 0)); return; } }