From patchwork Thu Jan 26 13:45:38 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Chouteau X-Patchwork-Id: 138094 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 06ADC1007D7 for ; Fri, 27 Jan 2012 12:05:57 +1100 (EST) Received: from localhost ([::1]:53388 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RqaGE-00058M-LN for incoming@patchwork.ozlabs.org; Thu, 26 Jan 2012 20:05:50 -0500 Received: from eggs.gnu.org ([140.186.70.92]:36770) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RqPe9-0002J3-0z for qemu-devel@nongnu.org; Thu, 26 Jan 2012 08:45:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RqPe2-0002D6-Od for qemu-devel@nongnu.org; Thu, 26 Jan 2012 08:45:48 -0500 Received: from mel.act-europe.fr ([194.98.77.210]:52710) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RqPe2-0002Cz-F4 for qemu-devel@nongnu.org; Thu, 26 Jan 2012 08:45:42 -0500 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id 691BB290040; Thu, 26 Jan 2012 14:45:42 +0100 (CET) X-Virus-Scanned: amavisd-new at eu.adacore.com Received: from mel.act-europe.fr ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 43fszAug9Pdz; Thu, 26 Jan 2012 14:45:42 +0100 (CET) Received: from PomPomGalli.act-europe.fr (pompomgalli.act-europe.fr [10.10.1.88]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mel.act-europe.fr (Postfix) with ESMTP id 0DD48CB3C60; Thu, 26 Jan 2012 14:45:42 +0100 (CET) From: Fabien Chouteau To: qemu-devel@nongnu.org Date: Thu, 26 Jan 2012 14:45:38 +0100 Message-Id: <1327585538-26367-1-git-send-email-chouteau@adacore.com> X-Mailer: git-send-email 1.7.4.1 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 194.98.77.210 X-Mailman-Approved-At: Thu, 26 Jan 2012 20:05:37 -0500 Cc: blauwirbel@gmail.com, avi@redhat.com, atar4qemu@gmail.com Subject: [Qemu-devel] [PATCH] GRLIB UART: Add RX channel X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch implements the RX channel of GRLIB UART with a FIFO to improve data rate. Signed-off-by: Fabien Chouteau --- hw/grlib_apbuart.c | 99 ++++++++++++++++++++++++++++++++++++++++++++++----- trace-events | 1 + 2 files changed, 90 insertions(+), 10 deletions(-) diff --git a/hw/grlib_apbuart.c b/hw/grlib_apbuart.c index f8a64e1..d30904c 100644 --- a/hw/grlib_apbuart.c +++ b/hw/grlib_apbuart.c @@ -24,7 +24,6 @@ #include "sysbus.h" #include "qemu-char.h" -#include "ptimer.h" #include "trace.h" @@ -66,6 +65,8 @@ #define SCALER_OFFSET 0x0C /* not supported */ #define FIFO_DEBUG_OFFSET 0x10 /* not supported */ +#define FIFO_LENGTH 1024 + typedef struct UART { SysBusDevice busdev; MemoryRegion iomem; @@ -77,21 +78,67 @@ typedef struct UART { uint32_t receive; uint32_t status; uint32_t control; + + /* FIFO */ + char buffer[FIFO_LENGTH]; + int len; + int current; } UART; +static int uart_data_to_read(UART *uart) +{ + return uart->current < uart->len; +} + +static char uart_pop(UART *uart) +{ + char ret; + + if (uart->len == 0) { + uart->status &= ~UART_DATA_READY; + return 0; + } + + ret = uart->buffer[uart->current++]; + + if (uart->current >= uart->len) { + /* Flush */ + uart->len = 0; + uart->current = 0; + } + + if (!uart_data_to_read(uart)) { + uart->status &= ~UART_DATA_READY; + } + + return ret; +} + +static void uart_add_to_fifo(UART *uart, + const uint8_t *buffer, + int length) +{ + if (uart->len + length > FIFO_LENGTH) { + abort(); + } + memcpy(uart->buffer + uart->len, buffer, length); + uart->len += length; +} + static int grlib_apbuart_can_receive(void *opaque) { UART *uart = opaque; - return !!(uart->status & UART_DATA_READY); + return FIFO_LENGTH - uart->len; } static void grlib_apbuart_receive(void *opaque, const uint8_t *buf, int size) { UART *uart = opaque; - uart->receive = *buf; - uart->status |= UART_DATA_READY; + uart_add_to_fifo(uart, buf, size); + + uart->status |= UART_DATA_READY; if (uart->control & UART_RECEIVE_INTERRUPT) { qemu_irq_pulse(uart->irq); @@ -103,9 +150,39 @@ static void grlib_apbuart_event(void *opaque, int event) trace_grlib_apbuart_event(event); } -static void -grlib_apbuart_write(void *opaque, target_phys_addr_t addr, - uint64_t value, unsigned size) + +static uint64_t grlib_apbuart_read(void *opaque, target_phys_addr_t addr, + unsigned size) +{ + UART *uart = opaque; + + addr &= 0xff; + + /* Unit registers */ + switch (addr) { + case DATA_OFFSET: + case DATA_OFFSET + 3: /* when only one byte read */ + return uart_pop(uart); + + case STATUS_OFFSET: + /* Read Only */ + return uart->status; + + case CONTROL_OFFSET: + return uart->control; + + case SCALER_OFFSET: + /* Not supported */ + return 0; + + default: + trace_grlib_apbuart_readl_unknown(addr); + return 0; + } +} + +static void grlib_apbuart_write(void *opaque, target_phys_addr_t addr, + uint64_t value, unsigned size) { UART *uart = opaque; unsigned char c = 0; @@ -115,6 +192,7 @@ grlib_apbuart_write(void *opaque, target_phys_addr_t addr, /* Unit registers */ switch (addr) { case DATA_OFFSET: + case DATA_OFFSET + 3: /* When only one byte write */ c = value & 0xFF; qemu_chr_fe_write(uart->chr, &c, 1); return; @@ -124,7 +202,7 @@ grlib_apbuart_write(void *opaque, target_phys_addr_t addr, return; case CONTROL_OFFSET: - /* Not supported */ + uart->control = value; return; case SCALER_OFFSET: @@ -141,18 +219,19 @@ grlib_apbuart_write(void *opaque, target_phys_addr_t addr, static bool grlib_apbuart_accepts(void *opaque, target_phys_addr_t addr, unsigned size, bool is_write) { - return is_write && size == 4; + return size <= 4; } static const MemoryRegionOps grlib_apbuart_ops = { .write = grlib_apbuart_write, + .read = grlib_apbuart_read, .valid.accepts = grlib_apbuart_accepts, .endianness = DEVICE_NATIVE_ENDIAN, }; static int grlib_apbuart_init(SysBusDevice *dev) { - UART *uart = FROM_SYSBUS(typeof(*uart), dev); + UART *uart = FROM_SYSBUS(typeof(*uart), dev); qemu_chr_add_handlers(uart->chr, grlib_apbuart_can_receive, diff --git a/trace-events b/trace-events index d2b0c61..5bb8bfb 100644 --- a/trace-events +++ b/trace-events @@ -340,6 +340,7 @@ grlib_irqmp_writel_unknown(uint64_t addr, uint32_t value) "addr 0x%"PRIx64" valu # hw/grlib_apbuart.c grlib_apbuart_event(int event) "event:%d" grlib_apbuart_writel_unknown(uint64_t addr, uint32_t value) "addr 0x%"PRIx64" value 0x%x" +grlib_apbuart_readl_unknown(uint64_t addr) "addr 0x%"PRIx64"" # hw/leon3.c leon3_set_irq(int intno) "Set CPU IRQ %d"