Patchwork [v9,5/9] ARM: exynos4210: Added PMU register model.

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Submitter Evgeny Voevodin
Date Jan. 20, 2012, 10:53 a.m.
Message ID <1327056829-24491-6-git-send-email-e.voevodin@samsung.com>
Download mbox | patch
Permalink /patch/137014/
State New
Headers show

Comments

Evgeny Voevodin - Jan. 20, 2012, 10:53 a.m.
From: Maksim Kozlov <m.kozlov@samsung.com>

This model just implements PMU registers as a bulk of memory.
The only reason of existence in such form is that secondary CPU
boot loader uses PMU INFORM5 register as a holding pen.

Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>
---
 Makefile.target     |    1 +
 hw/exynos4210.c     |    9 +
 hw/exynos4210_pmu.c |  549 +++++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 559 insertions(+), 0 deletions(-)
 create mode 100644 hw/exynos4210_pmu.c

Patch

diff --git a/Makefile.target b/Makefile.target
index 1914870..6cddf0c 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -341,6 +341,7 @@  obj-arm-y += versatile_pci.o
 obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
 obj-arm-y += exynos4210_gic.o exynos4210_combiner.o exynos4210.o
 obj-arm-y += exynos4_boards.o exynos4210_uart.o exynos4210_pwm.o
+obj-arm-y += exynos4210_pmu.o
 obj-arm-y += arm_l2x0.o
 obj-arm-y += arm_mptimer.o
 obj-arm-y += armv7m.o armv7m_nvic.o stellaris.o pl022.o stellaris_enet.o
diff --git a/hw/exynos4210.c b/hw/exynos4210.c
index ea5a1f8..2e2dbf0 100644
--- a/hw/exynos4210.c
+++ b/hw/exynos4210.c
@@ -52,6 +52,9 @@ 
 #define EXYNOS4210_EXT_COMBINER_BASE_ADDR   0x10440000
 #define EXYNOS4210_INT_COMBINER_BASE_ADDR   0x10448000
 
+/* PMU SFR base address */
+#define EXYNOS4210_PMU_BASE_ADDR            0x10020000
+
 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
                                     0x09, 0x00, 0x00, 0x00 };
 
@@ -204,6 +207,12 @@  Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
     memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR,
             &s->dram0_mem);
 
+   /* PMU.
+    * The only reason of existence at the moment is that secondary CPU boot
+    * loader uses PMU INFORM5 register as a holding pen.
+    */
+    sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL);
+
     /* PWM */
     sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR,
             irq_table[exynos4210_get_irq(22, 0)],
diff --git a/hw/exynos4210_pmu.c b/hw/exynos4210_pmu.c
new file mode 100644
index 0000000..235c3c3
--- /dev/null
+++ b/hw/exynos4210_pmu.c
@@ -0,0 +1,549 @@ 
+/*
+ *  exynos4210 Power Management Unit (PMU) Emulation
+ *
+ *  Copyright (C) 2011 Samsung Electronics Co Ltd.
+ *    Maksim Kozlov <m.kozlov@samsung.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License as published by the
+ *  Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * This model just implements PMU registers as a bulk of memory. The only reason
+ * of existence in such form is that secondary CPU boot loader uses PMU INFORM5
+ * register as a holding pen.
+ */
+
+#include "sysbus.h"
+
+#undef DEBUG_PMU
+#undef DEBUG_PMU_EXTEND
+
+//#define DEBUG_PMU
+//#define DEBUG_PMU_EXTEND
+
+#define  PRINT_DEBUG(fmt, args...)  \
+        do {} while (0)
+#define  PRINT_DEBUG_EXTEND(fmt, args...) \
+        do {} while (0)
+
+#ifdef DEBUG_PMU
+
+#undef PRINT_DEBUG
+#define  PRINT_DEBUG(fmt, args...)  \
+        do { \
+            fprintf(stderr, "  [%s:%d]   "fmt, __func__, __LINE__, ##args); \
+        } while (0)
+
+#ifdef DEBUG_PMU_EXTEND
+
+#undef PRINT_DEBUG_EXTEND
+#define  PRINT_DEBUG_EXTEND(fmt, args...) \
+        do { \
+            fprintf(stderr, "  [%s:%d]   "fmt, __func__, __LINE__, ##args); \
+        } while (0)
+
+#endif /* EXTEND */
+#endif
+
+/*
+ *  Offsets for PMU registers
+ */
+#define OM_STAT                  0x0000 /* OM status register */
+#define RTC_CLKO_SEL             0x000C /* Controls RTCCLKOUT */
+#define GNSS_RTC_OUT_CTRL        0x0010 /* Controls GNSS_RTC_OUT */
+#define SYSTEM_POWER_DOWN_CTRL   0x0200 /* Decides whether system-level
+                                           low-power mode is used. */
+#define SYSTEM_POWER_DOWN_OPTION 0x0208 /* Sets control options for
+                                           CENTRAL_SEQ */
+#define SWRESET                  0x0400 /* Generate software reset */
+#define RST_STAT                 0x0404 /* Reset status register */
+#define WAKEUP_STAT              0x0600 /* Wakeup status register  */
+#define EINT_WAKEUP_MASK         0x0604 /* Configure External INTerrupt mask */
+#define WAKEUP_MASK              0x0608 /* Configure wakeup source mask */
+#define HDMI_PHY_CONTROL         0x0700 /* HDMI PHY control register */
+#define USBDEVICE_PHY_CONTROL    0x0704 /* USB Device PHY control register */
+#define USBHOST_PHY_CONTROL      0x0708 /* USB HOST PHY control register */
+#define DAC_PHY_CONTROL          0x070C /* DAC control register  */
+#define MIPI_PHY0_CONTROL        0x0710 /* MIPI PHY control register */
+#define MIPI_PHY1_CONTROL        0x0714 /* MIPI PHY control register */
+#define ADC_PHY_CONTROL          0x0718 /* TS-ADC control register */
+#define PCIe_PHY_CONTROL         0x071C /* TS-PCIe control register */
+#define SATA_PHY_CONTROL         0x0720 /* TS-SATA control register */
+#define INFORM0                  0x0800 /* Information register 0  */
+#define INFORM1                  0x0804 /* Information register 1  */
+#define INFORM2                  0x0808 /* Information register 2  */
+#define INFORM3                  0x080C /* Information register 3  */
+#define INFORM4                  0x0810 /* Information register 4  */
+#define INFORM5                  0x0814 /* Information register 5  */
+#define INFORM6                  0x0818 /* Information register 6  */
+#define INFORM7                  0x081C /* Information register 7  */
+#define PMU_DEBUG                0x0A00 /* PMU debug register */
+#define ARM_CORE0_SYS_PWR_REG    0x1000 /* Sets system-level low-power option */
+#define ARM_CORE1_SYS_PWR_REG    0x1010 /* Sets system-level low-power option */
+#define ARM_COMMON_SYS_PWR_REG   0x1080 /* Sets system-level low-power option */
+#define ARM_CPU_L2_0_SYS_PWR_REG 0x10C0 /* Sets system-level low-power option */
+#define ARM_CPU_L2_1_SYS_PWR_REG 0x10C4 /* Sets system-level low-power option */
+#define CMU_ACLKSTOP_SYS_PWR_REG 0x1100 /* Sets system-level low-power option */
+#define CMU_SCLKSTOP_SYS_PWR_REG 0x1104 /* Sets system-level low-power option */
+#define CMU_RESET_SYS_PWR_REG    0x110C /* Sets system-level low-power option */
+#define APLL_SYSCLK_SYS_PWR_REG  0x1120 /* Sets system-level low-power option */
+#define MPLL_SYSCLK_SYS_PWR_REG  0x1124 /* Sets system-level low-power option */
+#define VPLL_SYSCLK_SYS_PWR_REG  0x1128 /* Sets system-level low-power option */
+#define EPLL_SYSCLK_SYS_PWR_REG  0x112C /* Sets system-level low-power option */
+#define CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG  0x1138 /* Sets system-level low-power
+                                                     option */
+#define CMU_RESET_GPS_ALIVE_SYS_PWR_REG    0x113C /* Sets system-level low-power
+                                                     option */
+#define CMU_CLKSTOP_CAM_SYS_PWR_REG 0x1140 /* Sets system-level low-power option
+ */
+#define CMU_CLKSTOP_TV_SYS_PWR_REG  0x1144 /* Sets system-level low-power option
+ */
+#define CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1148 /* Sets system-level low-power option
+ */
+#define CMU_CLKSTOP_G3D_SYS_PWR_REG 0x114C /* Sets system-level low-power option
+ */
+#define CMU_CLKSTOP_LCD0_SYS_PWR_REG 0x1150 /* Sets system-level low-power
+                                               option */
+#define CMU_CLKSTOP_LCD1_SYS_PWR_REG 0x1154 /* Sets system-level low-power
+                                               option */
+#define CMU_CLKSTOP_MAUDIO_SYS_PWR_REG 0x1158 /* Sets system-level low-power
+                                                 option */
+#define CMU_CLKSTOP_GPS_SYS_PWR_REG    0x115C /* Sets system-level low-power
+                                                 option */
+#define CMU_RESET_CAM_SYS_PWR_REG      0x1160 /* Sets system-level low-power
+                                                 option */
+#define CMU_RESET_TV_SYS_PWR_REG       0x1164 /* Sets system-level low-power
+                                                 option */
+#define CMU_RESET_MFC_SYS_PWR_REG      0x1168 /* Sets system-level low-power
+                                                 option */
+#define CMU_RESET_G3D_SYS_PWR_REG      0x116C /* Sets system-level low-power
+                                                 option */
+#define CMU_RESET_LCD0_SYS_PWR_REG     0x1170 /* Sets system-level low-power
+                                                 option */
+#define CMU_RESET_LCD1_SYS_PWR_REG     0x1174 /* Sets system-level low-power
+                                                 option */
+#define CMU_RESET_MAUDIO_SYS_PWR_REG   0x1178 /* Sets system-level low-power
+                                                 option */
+#define CMU_RESET_GPS_SYS_PWR_REG      0x117C /* Sets system-level low-power
+                                                 option */
+#define TOP_BUS_SYS_PWR_REG            0x1180 /* Sets system-level low-power
+                                                 option */
+#define TOP_RETENTION_SYS_PWR_REG      0x1184 /* Sets system-level low-power
+                                                 option */
+#define TOP_PWR_SYS_PWR_REG            0x1188 /* Sets system-level low-power
+                                                 option */
+#define LOGIC_RESET_SYS_PWR_REG        0x11A0 /* Sets system-level low-power
+                                                 option */
+#define OneNANDXL_MEM_SYS_PWR_REG      0x11C0 /* Sets system-level low-power
+                                                 option */
+#define MODEMIF_MEM_SYS_PWR_REG        0x11C4 /* Sets system-level low-power
+                                                 option */
+#define USBDEVICE_MEM_SYS_PWR_REG      0x11CC /* Sets system-level low-power
+                                                 option */
+#define SDMMC_MEM_SYS_PWR_REG   0x11D0 /* Sets system-level low-power
+                                          option */
+#define CSSYS_MEM_SYS_PWR_REG   0x11D4 /* Sets system-level low-power
+                                          option */
+#define SECSS_MEM_SYS_PWR_REG   0x11D8 /* Sets system-level low-power
+                                          option */
+#define PCIe_MEM_SYS_PWR_REG    0x11E0 /* Sets system-level low-power
+                                          option */
+#define SATA_MEM_SYS_PWR_REG    0x11E4 /* Sets system-level low-power
+                                          option */
+#define PAD_RETENTION_DRAM_SYS_PWR_REG     0x1200 /* Sets system-level low-power
+                                                     option */
+#define PAD_RETENTION_MAUDIO_SYS_PWR_REG   0x1204 /* Sets system-level low-power
+                                                     option */
+#define PAD_RETENTION_GPIO_SYS_PWR_REG     0x1220 /* Sets system-level low-power
+                                                     option */
+#define PAD_RETENTION_UART_SYS_PWR_REG     0x1224 /* Sets system-level low-power
+                                                     option */
+#define PAD_RETENTION_MMCA_SYS_PWR_REG     0x1228 /* Sets system-level low-power
+                                                     option */
+#define PAD_RETENTION_MMCB_SYS_PWR_REG     0x122C /* Sets system-level low-power
+                                                     option */
+#define PAD_RETENTION_EBIA_SYS_PWR_REG     0x1230 /* Sets system-level low-power
+                                                     option */
+#define PAD_RETENTION_EBIB_SYS_PWR_REG     0x1234 /* Sets system-level low-power
+                                                     option */
+#define PAD_ISOLATION_SYS_PWR_REG          0x1240 /* Sets system-level low-power
+                                                     option */
+#define PAD_ALV_SEL_SYS_PWR_REG 0x1260 /* Sets system-level low-power option */
+#define XUSBXTI_SYS_PWR_REG     0x1280 /* Sets system-level low-power option */
+#define XXTI_SYS_PWR_REG        0x1284 /* Sets system-level low-power option */
+#define EXT_REGULATOR_SYS_PWR_REG 0x12C0 /* Sets system-level low-power
+                                            option */
+#define GPIO_MODE_SYS_PWR_REG   0x1300 /* Sets system-level low-power option */
+#define GPIO_MODE_MAUDIO_SYS_PWR_REG 0x1340 /* Sets system-level low-power
+                                               option */
+#define CAM_SYS_PWR_REG         0x1380 /* Sets system-level low-power option */
+#define TV_SYS_PWR_REG          0x1384 /* Sets system-level low-power option */
+#define MFC_SYS_PWR_REG         0x1388 /* Sets system-level low-power option */
+#define G3D_SYS_PWR_REG         0x138C /* Sets system-level low-power option */
+#define LCD0_SYS_PWR_REG        0x1390 /* Sets system-level low-power option */
+#define LCD1_SYS_PWR_REG        0x1394 /* Sets system-level low-power option */
+#define MAUDIO_SYS_PWR_REG      0x1398 /* Sets system-level low-power option */
+#define GPS_SYS_PWR_REG         0x139C /* Sets system-level low-power option */
+#define GPS_ALIVE_SYS_PWR_REG   0x13A0 /* Sets system-level low-power option */
+#define ARM_CORE0_CONFIGURATION 0x2000 /* Configure power mode of ARM_CORE0 */
+#define ARM_CORE0_STATUS        0x2004 /* Check power mode of ARM_CORE0 */
+#define ARM_CORE0_OPTION        0x2008 /* Sets control options for ARM_CORE0 */
+#define ARM_CORE1_CONFIGURATION 0x2080 /* Configure power mode of ARM_CORE1 */
+#define ARM_CORE1_STATUS        0x2084 /* Check power mode of ARM_CORE1 */
+#define ARM_CORE1_OPTION        0x2088 /* Sets control options for ARM_CORE0 */
+#define ARM_COMMON_OPTION       0x2408 /* Sets control options for ARM_COMMON */
+#define ARM_CPU_L2_0_CONFIGURATION 0x2600 /* Configure power mode of
+                                             ARM_CPU_L2_0 */
+#define ARM_CPU_L2_0_STATUS     0x2604 /* Check power mode of ARM_CPU_L2_0 */
+#define ARM_CPU_L2_1_CONFIGURATION 0x2620 /* Configure power mode of
+                                             ARM_CPU_L2_1 */
+#define ARM_CPU_L2_1_STATUS     0x2624 /* Check power mode of ARM_CPU_L2_1 */
+#define PAD_RETENTION_MAUDIO_OPTION 0x3028 /* Sets control options for
+                                              PAD_RETENTION_MAUDIO */
+#define PAD_RETENTION_GPIO_OPTION   0x3108 /* Sets control options for
+                                              PAD_RETENTION_GPIO */
+#define PAD_RETENTION_UART_OPTION   0x3128 /* Sets control options for
+                                              PAD_RETENTION_UART */
+#define PAD_RETENTION_MMCA_OPTION   0x3148 /* Sets control options for
+                                              PAD_RETENTION_MMCA */
+#define PAD_RETENTION_MMCB_OPTION   0x3168 /* Sets control options for
+                                              PAD_RETENTION_MMCB */
+#define PAD_RETENTION_EBIA_OPTION   0x3188 /* Sets control options for
+                                              PAD_RETENTION_EBIA */
+#define PAD_RETENTION_EBIB_OPTION   0x31A8 /* Sets control options for
+                                              PAD_RETENTION_EBIB */
+#define PS_HOLD_CONTROL         0x330C /* PS_HOLD control register */
+#define XUSBXTI_CONFIGURATION   0x3400 /* Configure the pad of XUSBXTI */
+#define XUSBXTI_STATUS          0x3404 /* Check the pad of XUSBXTI */
+#define XUSBXTI_DURATION        0x341C /* Sets time required for XUSBXTI to be
+                                          stabilized */
+#define XXTI_CONFIGURATION      0x3420 /* Configure the pad of XXTI */
+#define XXTI_STATUS             0x3424 /* Check the pad of XXTI */
+#define XXTI_DURATION           0x343C /* Sets time required for XXTI to be
+                                          stabilized */
+#define EXT_REGULATOR_DURATION  0x361C /* Sets time required for EXT_REGULATOR
+                                          to be stabilized */
+#define CAM_CONFIGURATION       0x3C00 /* Configure power mode of CAM */
+#define CAM_STATUS              0x3C04 /* Check power mode of CAM */
+#define CAM_OPTION              0x3C08 /* Sets control options for CAM */
+#define TV_CONFIGURATION        0x3C20 /* Configure power mode of TV */
+#define TV_STATUS               0x3C24 /* Check power mode of TV */
+#define TV_OPTION               0x3C28 /* Sets control options for TV */
+#define MFC_CONFIGURATION       0x3C40 /* Configure power mode of MFC */
+#define MFC_STATUS              0x3C44 /* Check power mode of MFC */
+#define MFC_OPTION              0x3C48 /* Sets control options for MFC */
+#define G3D_CONFIGURATION       0x3C60 /* Configure power mode of G3D */
+#define G3D_STATUS              0x3C64 /* Check power mode of G3D */
+#define G3D_OPTION              0x3C68 /* Sets control options for G3D */
+#define LCD0_CONFIGURATION      0x3C80 /* Configure power mode of LCD0 */
+#define LCD0_STATUS             0x3C84 /* Check power mode of LCD0 */
+#define LCD0_OPTION             0x3C88 /* Sets control options for LCD0 */
+#define LCD1_CONFIGURATION      0x3CA0 /* Configure power mode of LCD1 */
+#define LCD1_STATUS             0x3CA4 /* Check power mode of LCD1 */
+#define LCD1_OPTION             0x3CA8 /* Sets control options for LCD1 */
+#define GPS_CONFIGURATION       0x3CE0 /* Configure power mode of GPS */
+#define GPS_STATUS              0x3CE4 /* Check power mode of GPS */
+#define GPS_OPTION              0x3CE8 /* Sets control options for GPS */
+#define GPS_ALIVE_CONFIGURATION 0x3D00 /* Configure power mode of GPS */
+#define GPS_ALIVE_STATUS        0x3D04 /* Check power mode of GPS */
+#define GPS_ALIVE_OPTION        0x3D08 /* Sets control options for GPS */
+
+#define EXYNOS4210_PMU_REGS_MEM_SIZE 0x3d0c
+
+typedef struct Exynos4210PmuReg {
+    const char  *name; /* the only reason is the debug output */
+    uint32_t     offset;
+    uint32_t     reset_value;
+} Exynos4210PmuReg;
+
+static const Exynos4210PmuReg exynos4210_pmu_regs[] = {
+    {"OM_STAT", OM_STAT, 0x00000000},
+    {"RTC_CLKO_SEL", RTC_CLKO_SEL, 0x00000000},
+    {"GNSS_RTC_OUT_CTRL", GNSS_RTC_OUT_CTRL, 0x00000001},
+    {"SYSTEM_POWER_DOWN_CTRL", SYSTEM_POWER_DOWN_CTRL, 0x00010000},
+    {"SYSTEM_POWER_DOWN_OPTION", SYSTEM_POWER_DOWN_OPTION, 0x03030000},
+    {"SWRESET", SWRESET, 0x00000000},
+    {"RST_STAT", RST_STAT, 0x00000000},
+    {"WAKEUP_STAT", WAKEUP_STAT, 0x00000000},
+    {"EINT_WAKEUP_MASK", EINT_WAKEUP_MASK, 0x00000000},
+    {"WAKEUP_MASK", WAKEUP_MASK, 0x00000000},
+    {"HDMI_PHY_CONTROL", HDMI_PHY_CONTROL, 0x00960000},
+    {"USBDEVICE_PHY_CONTROL", USBDEVICE_PHY_CONTROL, 0x00000000},
+    {"USBHOST_PHY_CONTROL", USBHOST_PHY_CONTROL, 0x00000000},
+    {"DAC_PHY_CONTROL", DAC_PHY_CONTROL, 0x00000000},
+    {"MIPI_PHY0_CONTROL", MIPI_PHY0_CONTROL, 0x00000000},
+    {"MIPI_PHY1_CONTROL", MIPI_PHY1_CONTROL, 0x00000000},
+    {"ADC_PHY_CONTROL", ADC_PHY_CONTROL, 0x00000001},
+    {"PCIe_PHY_CONTROL", PCIe_PHY_CONTROL, 0x00000000},
+    {"SATA_PHY_CONTROL", SATA_PHY_CONTROL, 0x00000000},
+    {"INFORM0", INFORM0, 0x00000000},
+    {"INFORM1", INFORM1, 0x00000000},
+    {"INFORM2", INFORM2, 0x00000000},
+    {"INFORM3", INFORM3, 0x00000000},
+    {"INFORM4", INFORM4, 0x00000000},
+    {"INFORM5", INFORM5, 0x00000000},
+    {"INFORM6", INFORM6, 0x00000000},
+    {"INFORM7", INFORM7, 0x00000000},
+    {"PMU_DEBUG", PMU_DEBUG, 0x00000000},
+    {"ARM_CORE0_SYS_PWR_REG", ARM_CORE0_SYS_PWR_REG, 0xFFFFFFFF},
+    {"ARM_CORE1_SYS_PWR_REG", ARM_CORE1_SYS_PWR_REG, 0xFFFFFFFF},
+    {"ARM_COMMON_SYS_PWR_REG", ARM_COMMON_SYS_PWR_REG, 0xFFFFFFFF},
+    {"ARM_CPU_L2_0_SYS_PWR_REG", ARM_CPU_L2_0_SYS_PWR_REG, 0xFFFFFFFF},
+    {"ARM_CPU_L2_1_SYS_PWR_REG", ARM_CPU_L2_1_SYS_PWR_REG, 0xFFFFFFFF},
+    {"CMU_ACLKSTOP_SYS_PWR_REG", CMU_ACLKSTOP_SYS_PWR_REG, 0xFFFFFFFF},
+    {"CMU_SCLKSTOP_SYS_PWR_REG", CMU_SCLKSTOP_SYS_PWR_REG, 0xFFFFFFFF},
+    {"CMU_RESET_SYS_PWR_REG", CMU_RESET_SYS_PWR_REG, 0xFFFFFFFF},
+    {"APLL_SYSCLK_SYS_PWR_REG", APLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF},
+    {"MPLL_SYSCLK_SYS_PWR_REG", MPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF},
+    {"VPLL_SYSCLK_SYS_PWR_REG", VPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF},
+    {"EPLL_SYSCLK_SYS_PWR_REG", EPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF},
+    {"CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG", CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG,
+            0xFFFFFFFF},
+    {"CMU_RESET_GPS_ALIVE_SYS_PWR_REG", CMU_RESET_GPS_ALIVE_SYS_PWR_REG,
+            0xFFFFFFFF},
+    {"CMU_CLKSTOP_CAM_SYS_PWR_REG", CMU_CLKSTOP_CAM_SYS_PWR_REG, 0xFFFFFFFF},
+    {"CMU_CLKSTOP_TV_SYS_PWR_REG", CMU_CLKSTOP_TV_SYS_PWR_REG, 0xFFFFFFFF},
+    {"CMU_CLKSTOP_MFC_SYS_PWR_REG", CMU_CLKSTOP_MFC_SYS_PWR_REG, 0xFFFFFFFF},
+    {"CMU_CLKSTOP_G3D_SYS_PWR_REG", CMU_CLKSTOP_G3D_SYS_PWR_REG, 0xFFFFFFFF},
+    {"CMU_CLKSTOP_LCD0_SYS_PWR_REG", CMU_CLKSTOP_LCD0_SYS_PWR_REG, 0xFFFFFFFF},
+    {"CMU_CLKSTOP_LCD1_SYS_PWR_REG", CMU_CLKSTOP_LCD1_SYS_PWR_REG, 0xFFFFFFFF},
+    {"CMU_CLKSTOP_MAUDIO_SYS_PWR_REG", CMU_CLKSTOP_MAUDIO_SYS_PWR_REG,
+            0xFFFFFFFF},
+    {"CMU_CLKSTOP_GPS_SYS_PWR_REG", CMU_CLKSTOP_GPS_SYS_PWR_REG, 0xFFFFFFFF},
+    {"CMU_RESET_CAM_SYS_PWR_REG", CMU_RESET_CAM_SYS_PWR_REG, 0xFFFFFFFF},
+    {"CMU_RESET_TV_SYS_PWR_REG", CMU_RESET_TV_SYS_PWR_REG, 0xFFFFFFFF},
+    {"CMU_RESET_MFC_SYS_PWR_REG", CMU_RESET_MFC_SYS_PWR_REG, 0xFFFFFFFF},
+    {"CMU_RESET_G3D_SYS_PWR_REG", CMU_RESET_G3D_SYS_PWR_REG, 0xFFFFFFFF},
+    {"CMU_RESET_LCD0_SYS_PWR_REG", CMU_RESET_LCD0_SYS_PWR_REG, 0xFFFFFFFF},
+    {"CMU_RESET_LCD1_SYS_PWR_REG", CMU_RESET_LCD1_SYS_PWR_REG, 0xFFFFFFFF},
+    {"CMU_RESET_MAUDIO_SYS_PWR_REG", CMU_RESET_MAUDIO_SYS_PWR_REG, 0xFFFFFFFF},
+    {"CMU_RESET_GPS_SYS_PWR_REG", CMU_RESET_GPS_SYS_PWR_REG, 0xFFFFFFFF},
+    {"TOP_BUS_SYS_PWR_REG", TOP_BUS_SYS_PWR_REG, 0xFFFFFFFF},
+    {"TOP_RETENTION_SYS_PWR_REG", TOP_RETENTION_SYS_PWR_REG, 0xFFFFFFFF},
+    {"TOP_PWR_SYS_PWR_REG", TOP_PWR_SYS_PWR_REG, 0xFFFFFFFF},
+    {"LOGIC_RESET_SYS_PWR_REG", LOGIC_RESET_SYS_PWR_REG, 0xFFFFFFFF},
+    {"OneNANDXL_MEM_SYS_PWR_REG", OneNANDXL_MEM_SYS_PWR_REG, 0xFFFFFFFF},
+    {"MODEMIF_MEM_SYS_PWR_REG", MODEMIF_MEM_SYS_PWR_REG, 0xFFFFFFFF},
+    {"USBDEVICE_MEM_SYS_PWR_REG", USBDEVICE_MEM_SYS_PWR_REG, 0xFFFFFFFF},
+    {"SDMMC_MEM_SYS_PWR_REG", SDMMC_MEM_SYS_PWR_REG, 0xFFFFFFFF},
+    {"CSSYS_MEM_SYS_PWR_REG", CSSYS_MEM_SYS_PWR_REG, 0xFFFFFFFF},
+    {"SECSS_MEM_SYS_PWR_REG", SECSS_MEM_SYS_PWR_REG, 0xFFFFFFFF},
+    {"PCIe_MEM_SYS_PWR_REG", PCIe_MEM_SYS_PWR_REG, 0xFFFFFFFF},
+    {"SATA_MEM_SYS_PWR_REG", SATA_MEM_SYS_PWR_REG, 0xFFFFFFFF},
+    {"PAD_RETENTION_DRAM_SYS_PWR_REG", PAD_RETENTION_DRAM_SYS_PWR_REG,
+            0xFFFFFFFF},
+    {"PAD_RETENTION_MAUDIO_SYS_PWR_REG", PAD_RETENTION_MAUDIO_SYS_PWR_REG,
+            0xFFFFFFFF},
+    {"PAD_RETENTION_GPIO_SYS_PWR_REG", PAD_RETENTION_GPIO_SYS_PWR_REG,
+            0xFFFFFFFF},
+    {"PAD_RETENTION_UART_SYS_PWR_REG", PAD_RETENTION_UART_SYS_PWR_REG,
+            0xFFFFFFFF},
+    {"PAD_RETENTION_MMCA_SYS_PWR_REG", PAD_RETENTION_MMCA_SYS_PWR_REG,
+            0xFFFFFFFF},
+    {"PAD_RETENTION_MMCB_SYS_PWR_REG", PAD_RETENTION_MMCB_SYS_PWR_REG,
+            0xFFFFFFFF},
+    {"PAD_RETENTION_EBIA_SYS_PWR_REG", PAD_RETENTION_EBIA_SYS_PWR_REG,
+            0xFFFFFFFF},
+    {"PAD_RETENTION_EBIB_SYS_PWR_REG", PAD_RETENTION_EBIB_SYS_PWR_REG,
+            0xFFFFFFFF},
+    {"PAD_ISOLATION_SYS_PWR_REG", PAD_ISOLATION_SYS_PWR_REG, 0xFFFFFFFF},
+    {"PAD_ALV_SEL_SYS_PWR_REG", PAD_ALV_SEL_SYS_PWR_REG, 0xFFFFFFFF},
+    {"XUSBXTI_SYS_PWR_REG", XUSBXTI_SYS_PWR_REG, 0xFFFFFFFF},
+    {"XXTI_SYS_PWR_REG", XXTI_SYS_PWR_REG, 0xFFFFFFFF},
+    {"EXT_REGULATOR_SYS_PWR_REG", EXT_REGULATOR_SYS_PWR_REG, 0xFFFFFFFF},
+    {"GPIO_MODE_SYS_PWR_REG", GPIO_MODE_SYS_PWR_REG, 0xFFFFFFFF},
+    {"GPIO_MODE_MAUDIO_SYS_PWR_REG", GPIO_MODE_MAUDIO_SYS_PWR_REG, 0xFFFFFFFF},
+    {"CAM_SYS_PWR_REG", CAM_SYS_PWR_REG, 0xFFFFFFFF},
+    {"TV_SYS_PWR_REG", TV_SYS_PWR_REG, 0xFFFFFFFF},
+    {"MFC_SYS_PWR_REG", MFC_SYS_PWR_REG, 0xFFFFFFFF},
+    {"G3D_SYS_PWR_REG", G3D_SYS_PWR_REG, 0xFFFFFFFF},
+    {"LCD0_SYS_PWR_REG", LCD0_SYS_PWR_REG, 0xFFFFFFFF},
+    {"LCD1_SYS_PWR_REG", LCD1_SYS_PWR_REG, 0xFFFFFFFF},
+    {"MAUDIO_SYS_PWR_REG", MAUDIO_SYS_PWR_REG, 0xFFFFFFFF},
+    {"GPS_SYS_PWR_REG", GPS_SYS_PWR_REG, 0xFFFFFFFF},
+    {"GPS_ALIVE_SYS_PWR_REG", GPS_ALIVE_SYS_PWR_REG, 0xFFFFFFFF},
+    {"ARM_CORE0_CONFIGURATION", ARM_CORE0_CONFIGURATION, 0x00000003},
+    {"ARM_CORE0_STATUS", ARM_CORE0_STATUS, 0x00030003},
+    {"ARM_CORE0_OPTION", ARM_CORE0_OPTION, 0x01010001},
+    {"ARM_CORE1_CONFIGURATION", ARM_CORE1_CONFIGURATION, 0x00000003},
+    {"ARM_CORE1_STATUS", ARM_CORE1_STATUS, 0x00030003},
+    {"ARM_CORE1_OPTION", ARM_CORE1_OPTION, 0x01010001},
+    {"ARM_COMMON_OPTION", ARM_COMMON_OPTION, 0x00000001},
+    {"ARM_CPU_L2_0_CONFIGURATION", ARM_CPU_L2_0_CONFIGURATION, 0x00000003},
+    {"ARM_CPU_L2_0_STATUS", ARM_CPU_L2_0_STATUS, 0x00000003},
+    {"ARM_CPU_L2_1_CONFIGURATION", ARM_CPU_L2_1_CONFIGURATION, 0x00000003},
+    {"ARM_CPU_L2_1_STATUS", ARM_CPU_L2_1_STATUS, 0x00000003},
+    {"PAD_RETENTION_MAUDIO_OPTION", PAD_RETENTION_MAUDIO_OPTION, 0x00000000},
+    {"PAD_RETENTION_GPIO_OPTION", PAD_RETENTION_GPIO_OPTION, 0x00000000},
+    {"PAD_RETENTION_UART_OPTION", PAD_RETENTION_UART_OPTION, 0x00000000},
+    {"PAD_RETENTION_MMCA_OPTION", PAD_RETENTION_MMCA_OPTION, 0x00000000},
+    {"PAD_RETENTION_MMCB_OPTION", PAD_RETENTION_MMCB_OPTION, 0x00000000},
+    {"PAD_RETENTION_EBIA_OPTION", PAD_RETENTION_EBIA_OPTION, 0x00000000},
+    {"PAD_RETENTION_EBIB_OPTION", PAD_RETENTION_EBIB_OPTION, 0x00000000},
+    {"PS_HOLD_CONTROL", PS_HOLD_CONTROL, 0x00005200},
+    {"XUSBXTI_CONFIGURATION", XUSBXTI_CONFIGURATION, 0x00000001},
+    {"XUSBXTI_STATUS", XUSBXTI_STATUS, 0x00000001},
+    {"XUSBXTI_DURATION", XUSBXTI_DURATION, 0xFFF00000},
+    {"XXTI_CONFIGURATION", XXTI_CONFIGURATION, 0x00000001},
+    {"XXTI_STATUS", XXTI_STATUS, 0x00000001},
+    {"XXTI_DURATION", XXTI_DURATION, 0xFFF00000},
+    {"EXT_REGULATOR_DURATION", EXT_REGULATOR_DURATION, 0xFFF03FFF},
+    {"CAM_CONFIGURATION", CAM_CONFIGURATION, 0x00000007},
+    {"CAM_STATUS", CAM_STATUS, 0x00060007},
+    {"CAM_OPTION", CAM_OPTION, 0x00000001},
+    {"TV_CONFIGURATION", TV_CONFIGURATION, 0x00000007},
+    {"TV_STATUS", TV_STATUS, 0x00060007},
+    {"TV_OPTION", TV_OPTION, 0x00000001},
+    {"MFC_CONFIGURATION", MFC_CONFIGURATION, 0x00000007},
+    {"MFC_STATUS", MFC_STATUS, 0x00060007},
+    {"MFC_OPTION", MFC_OPTION, 0x00000001},
+    {"G3D_CONFIGURATION", G3D_CONFIGURATION, 0x00000007},
+    {"G3D_STATUS", G3D_STATUS, 0x00060007},
+    {"G3D_OPTION", G3D_OPTION, 0x00000001},
+    {"LCD0_CONFIGURATION", LCD0_CONFIGURATION, 0x00000007},
+    {"LCD0_STATUS", LCD0_STATUS, 0x00060007},
+    {"LCD0_OPTION", LCD0_OPTION, 0x00000001},
+    {"LCD1_CONFIGURATION", LCD1_CONFIGURATION, 0x00000007},
+    {"LCD1_STATUS", LCD1_STATUS, 0x00060007},
+    {"LCD1_OPTION", LCD1_OPTION, 0x00000001},
+    {"GPS_CONFIGURATION", GPS_CONFIGURATION, 0x00000007},
+    {"GPS_STATUS", GPS_STATUS, 0x00060007},
+    {"GPS_OPTION", GPS_OPTION, 0x00000001},
+    {"GPS_ALIVE_CONFIGURATION", GPS_ALIVE_CONFIGURATION, 0x00000007},
+    {"GPS_ALIVE_STATUS", GPS_ALIVE_STATUS, 0x00060007},
+    {"GPS_ALIVE_OPTION", GPS_ALIVE_OPTION, 0x00000001},
+};
+
+/*
+ * for indexing register in the uint32_t array
+ *
+ * 'reg' - register offset (see offsets definitions above)
+ *
+ */
+#define I_(reg) (reg / sizeof(uint32_t))
+
+typedef struct Exynos4210PmuState {
+    SysBusDevice busdev;
+    MemoryRegion iomem;
+    uint32_t reg[EXYNOS4210_PMU_REGS_MEM_SIZE];
+} Exynos4210PmuState;
+
+#ifdef DEBUG_PMU
+/* The only meaning of life - debugging. This functions should be only used
+ * inside PRINT_DEBUG_... macros
+ */
+static const char *exynos4210_pmu_regname(target_phys_addr_t  offset)
+{
+    int regs_number = sizeof(exynos4210_pmu_regs) / sizeof(Exynos4210PmuReg);
+    int i;
+
+    for (i = 0; i < regs_number; i++) {
+        if (offset == exynos4210_pmu_regs[i].offset) {
+            return exynos4210_pmu_regs[i].name;
+        }
+    }
+
+    return NULL;
+}
+#endif
+
+static uint64_t exynos4210_pmu_read(void *opaque, target_phys_addr_t offset,
+                                    unsigned size)
+{
+    Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
+
+    if (offset > (EXYNOS4210_PMU_REGS_MEM_SIZE - sizeof(uint32_t))) {
+        hw_error("%s: Bad offset 0x%x\n", __func__, (int)offset);
+    }
+
+#ifdef DEBUG_PMU
+    if (exynos4210_pmu_regname(offset)) {
+        PRINT_DEBUG_EXTEND("%s [0x%04x] -> %08x\n",
+                           exynos4210_pmu_regname(offset),
+                           offset, s->reg[I_(offset)]);
+    } else {
+        PRINT_DEBUG_EXTEND("Bad offset 0x%x\n", (int)offset);
+    }
+#endif
+    return s->reg[I_(offset)];
+}
+
+
+static void exynos4210_pmu_write(void *opaque, target_phys_addr_t offset,
+                                 uint64_t val, unsigned size)
+{
+    Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
+
+    if (offset > (EXYNOS4210_PMU_REGS_MEM_SIZE - sizeof(uint32_t))) {
+        hw_error("%s: Bad offset 0x%x\n", __func__, (int)offset);
+    }
+
+    s->reg[I_(offset)] = val;
+#ifdef DEBUG_PMU
+    if (exynos4210_pmu_regname(offset)) {
+        PRINT_DEBUG_EXTEND("%s <0x%04x> <- %08x\n",
+                           exynos4210_pmu_regname(offset),
+                           offset, s->reg[I_(offset)]);
+    } else {
+        PRINT_DEBUG_EXTEND("Bad offset 0x%x\n", (int)offset);
+    }
+#endif
+
+}
+
+
+static const MemoryRegionOps exynos4210_pmu_ops = {
+    .read = exynos4210_pmu_read,
+    .write = exynos4210_pmu_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+
+static void exynos4210_pmu_reset(void *opaque)
+{
+    Exynos4210PmuState *s = (Exynos4210PmuState *)opaque;
+    int regs_number = sizeof(exynos4210_pmu_regs) / sizeof(Exynos4210PmuReg);
+    int i;
+
+    /* Set default values for registers */
+    for (i = 0; i < regs_number; i++) {
+        s->reg[I_(exynos4210_pmu_regs[i].offset)] =
+                exynos4210_pmu_regs[i].reset_value;
+    }
+}
+
+static int exynos4210_pmu_init(SysBusDevice *dev)
+{
+    Exynos4210PmuState *s = FROM_SYSBUS(Exynos4210PmuState, dev);
+
+    /* memory mapping */
+    memory_region_init_io(&s->iomem, &exynos4210_pmu_ops, s, "exynos4210.pmu",
+                          EXYNOS4210_PMU_REGS_MEM_SIZE);
+    sysbus_init_mmio(dev, &s->iomem);
+
+    qemu_register_reset(exynos4210_pmu_reset, s);
+
+    exynos4210_pmu_reset(s);
+
+    return 0;
+}
+
+static void exynos4210_pmu_register(void)
+{
+    sysbus_register_dev("exynos4210.pmu", sizeof(Exynos4210PmuState),
+                        exynos4210_pmu_init);
+}
+
+
+device_init(exynos4210_pmu_register)