From patchwork Thu Jan 19 11:24:59 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Kiszka X-Patchwork-Id: 136833 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id BEF2CB6EE6 for ; Thu, 19 Jan 2012 23:29:16 +1100 (EST) Received: from localhost ([::1]:48183 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rnq8V-0004M9-0D for incoming@patchwork.ozlabs.org; Thu, 19 Jan 2012 06:26:31 -0500 Received: from eggs.gnu.org ([140.186.70.92]:50321) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rnq7V-0002i5-5V for qemu-devel@nongnu.org; Thu, 19 Jan 2012 06:25:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rnq7P-0008CX-QA for qemu-devel@nongnu.org; Thu, 19 Jan 2012 06:25:29 -0500 Received: from thoth.sbs.de ([192.35.17.2]:27999) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rnq7P-0008Az-Fw for qemu-devel@nongnu.org; Thu, 19 Jan 2012 06:25:23 -0500 Received: from mail1.siemens.de (localhost [127.0.0.1]) by thoth.sbs.de (8.13.6/8.13.6) with ESMTP id q0JBPEw6020765; Thu, 19 Jan 2012 12:25:14 +0100 Received: from mchn199C.mchp.siemens.de ([139.25.109.49]) by mail1.siemens.de (8.13.6/8.13.6) with ESMTP id q0JBPAMM027843; Thu, 19 Jan 2012 12:25:14 +0100 From: Jan Kiszka To: Avi Kivity , Marcelo Tosatti Date: Thu, 19 Jan 2012 12:24:59 +0100 Message-Id: <7a380ca350f84b5b99391da20a2b4ea505b0524d.1326972302.git.jan.kiszka@siemens.com> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) X-Received-From: 192.35.17.2 Cc: Blue Swirl , Anthony Liguori , qemu-devel , kvm@vger.kernel.org, "Michael S. Tsirkin" Subject: [Qemu-devel] [PATCH v8 07/18] apic: Open-code timer save/restore X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org To enable migration between accelerated and non-accelerated APIC models, we will need to handle the timer saving and restoring specially and can no longer rely on the automatics of VMSTATE_TIMER. Specifically, accelerated model will not start any QEMUTimer. This patch therefore factors out the generic bits into apic_next_timer and use a post-load callback to implemented model-specific logic. Signed-off-by: Jan Kiszka --- hw/apic.c | 30 +++++++++++----------------- hw/apic_common.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++- hw/apic_internal.h | 3 ++ 3 files changed, 67 insertions(+), 20 deletions(-) diff --git a/hw/apic.c b/hw/apic.c index 387a469..e59c964 100644 --- a/hw/apic.c +++ b/hw/apic.c @@ -521,25 +521,9 @@ static uint32_t apic_get_current_count(APICCommonState *s) static void apic_timer_update(APICCommonState *s, int64_t current_time) { - int64_t next_time, d; - - if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) { - d = (current_time - s->initial_count_load_time) >> - s->count_shift; - if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { - if (!s->initial_count) - goto no_timer; - d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1); - } else { - if (d >= s->initial_count) - goto no_timer; - d = (uint64_t)s->initial_count + 1; - } - next_time = s->initial_count_load_time + (d << s->count_shift); - qemu_mod_timer(s->timer, next_time); - s->next_time = next_time; + if (apic_next_timer(s, current_time)) { + qemu_mod_timer(s->timer, s->next_time); } else { - no_timer: qemu_del_timer(s->timer); } } @@ -753,6 +737,15 @@ static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) } } +static void apic_post_load(APICCommonState *s) +{ + if (s->timer_expiry != -1) { + qemu_mod_timer(s->timer, s->timer_expiry); + } else { + qemu_del_timer(s->timer); + } +} + static const MemoryRegionOps apic_io_ops = { .old_mmio = { .read = { apic_mem_readb, apic_mem_readw, apic_mem_readl, }, @@ -776,6 +769,7 @@ static APICCommonInfo apic_info = { .set_base = apic_set_base, .set_tpr = apic_set_tpr, .external_nmi = apic_external_nmi, + .post_load = apic_post_load, }; static void apic_register_devices(void) diff --git a/hw/apic_common.c b/hw/apic_common.c index eef977f..e05369c 100644 --- a/hw/apic_common.c +++ b/hw/apic_common.c @@ -93,6 +93,39 @@ void apic_deliver_nmi(DeviceState *d) info->external_nmi(s); } +bool apic_next_timer(APICCommonState *s, int64_t current_time) +{ + int64_t d; + + /* We need to store the timer state separately to support APIC + * implementations that maintain a non-QEMU timer, e.g. inside the + * host kernel. This open-coded state allows us to migrate between + * both models. */ + s->timer_expiry = -1; + + if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) { + return false; + } + + d = (current_time - s->initial_count_load_time) >> s->count_shift; + + if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) { + if (!s->initial_count) { + return false; + } + d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * + ((uint64_t)s->initial_count + 1); + } else { + if (d >= s->initial_count) { + return false; + } + d = (uint64_t)s->initial_count + 1; + } + s->next_time = s->initial_count_load_time + (d << s->count_shift); + s->timer_expiry = s->next_time; + return true; +} + void apic_init_reset(DeviceState *d) { APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); @@ -120,7 +153,10 @@ void apic_init_reset(DeviceState *d) s->next_time = 0; s->wait_for_sipi = 1; - qemu_del_timer(s->timer); + if (s->timer) { + qemu_del_timer(s->timer); + } + s->timer_expiry = -1; } static void apic_reset_common(DeviceState *d) @@ -203,12 +239,25 @@ static int apic_init_common(SysBusDevice *dev) return 0; } +static int apic_dispatch_post_load(void *opaque, int version_id) +{ + APICCommonState *s = opaque; + APICCommonInfo *info = + DO_UPCAST(APICCommonInfo, busdev.qdev, s->busdev.qdev.info); + + if (info->post_load) { + info->post_load(s); + } + return 0; +} + static const VMStateDescription vmstate_apic_common = { .name = "apic", .version_id = 3, .minimum_version_id = 3, .minimum_version_id_old = 1, .load_state_old = apic_load_old, + .post_load = apic_dispatch_post_load, .fields = (VMStateField[]) { VMSTATE_UINT32(apicbase, APICCommonState), VMSTATE_UINT8(id, APICCommonState), @@ -228,7 +277,8 @@ static const VMStateDescription vmstate_apic_common = { VMSTATE_UINT32(initial_count, APICCommonState), VMSTATE_INT64(initial_count_load_time, APICCommonState), VMSTATE_INT64(next_time, APICCommonState), - VMSTATE_TIMER(timer, APICCommonState), + VMSTATE_INT64(timer_expiry, + APICCommonState), /* open-coded timer state */ VMSTATE_END_OF_LIST() } }; diff --git a/hw/apic_internal.h b/hw/apic_internal.h index a7433fb..1db4f06 100644 --- a/hw/apic_internal.h +++ b/hw/apic_internal.h @@ -92,6 +92,7 @@ struct APICCommonState { int64_t next_time; int idx; QEMUTimer *timer; + int64_t timer_expiry; int sipi_vector; int wait_for_sipi; }; @@ -104,9 +105,11 @@ struct APICCommonInfo { void (*set_base)(APICCommonState *s, uint64_t val); void (*set_tpr)(APICCommonState *s, uint8_t val); void (*external_nmi)(APICCommonState *s); + void (*post_load)(APICCommonState *s); }; void apic_report_irq_delivered(int delivered); void apic_qdev_register(APICCommonInfo *info); +bool apic_next_timer(APICCommonState *s, int64_t current_time); #endif /* !QEMU_APIC_INTERNAL_H */