From patchwork Fri Jan 13 08:56:16 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Behme Dirk (CM/ESO2)" X-Patchwork-Id: 135744 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id DF525B6F7E for ; Fri, 13 Jan 2012 19:56:29 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BFF3728316; Fri, 13 Jan 2012 09:56:26 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id dwYD00Bzfd60; Fri, 13 Jan 2012 09:56:26 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id F1042285B5; Fri, 13 Jan 2012 09:56:24 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2AD43285B5 for ; Fri, 13 Jan 2012 09:56:24 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id rKYuxFhXn7qb for ; Fri, 13 Jan 2012 09:56:22 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from smtp2-v.fe.bosch.de (smtp2-v.fe.bosch.de [139.15.237.6]) by theia.denx.de (Postfix) with ESMTPS id 9C2DA28316 for ; Fri, 13 Jan 2012 09:56:21 +0100 (CET) Received: from vsmta12.fe.internet.bosch.com (unknown [10.4.98.30]) by imta24.fe.bosch.de (Postfix) with ESMTP id 3E7ECB3B87AE for ; Fri, 13 Jan 2012 09:55:59 +0100 (CET) Received: from localhost (vsgw2.fe.internet.bosch.com [10.4.98.13]) by vsmta12.fe.internet.bosch.com (Postfix) with SMTP id E211B121004A for ; Fri, 13 Jan 2012 09:56:20 +0100 (CET) Received: from SI-HUB1001.de.bosch.com (10.4.103.108) by si-hub05.de.bosch.com (10.3.153.47) with Microsoft SMTP Server (TLS) id 8.3.213.0; Fri, 13 Jan 2012 09:56:18 +0100 Received: from hi-z5661.hi.de.bosch.com (10.34.217.179) by SI-HUB1001.de.bosch.com (10.4.103.108) with Microsoft SMTP Server id 14.1.355.2; Fri, 13 Jan 2012 09:56:18 +0100 Received: from localhost.localdomain (localhost [127.0.0.1]) by hi-z5661.hi.de.bosch.com (Postfix) with ESMTP id 6C4074019F; Fri, 13 Jan 2012 09:56:18 +0100 (CET) From: Dirk Behme To: Date: Fri, 13 Jan 2012 09:56:16 +0100 Message-ID: <1326444976-5492-1-git-send-email-dirk.behme@de.bosch.com> X-Mailer: git-send-email 1.7.0.4 MIME-Version: 1.0 Cc: Jason Liu , Eric Miao Subject: [U-Boot] [PATCH] i.mx6q: mx6qsabrelite: Add the ethernet function support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Jason Liu Signed-off-by: Jason Liu Signed-off-by: Eric Miao CC: Jason Liu CC: Stefano Babic --- Note: This patch is against the recent head of u-boot-imx.git including the SabreLite support: 5b894e4d00ff94a221f8cc23d54d08b889f54190 i.mx: i.mx6q: add the initial support for i.mx6q Sabre Lite board Note: tools/checkpatch.pl reports: total: 0 errors, 0 warnings, 157 lines checked NOTE: Ignored message types: COMPLEX_MACRO CONSIDER_KSTRTO MINMAX MULTISTATEMENT_MACRO_USE_DO_WHILE 0001-i.mx6q-mx6qsabrelite-Add-the-ethernet-function-suppo.patch has no obvious style problems and is ready for submission. board/freescale/mx6qsabrelite/mx6qsabrelite.c | 108 +++++++++++++++++++++++++ include/configs/mx6qsabrelite.h | 13 +++- 2 files changed, 119 insertions(+), 2 deletions(-) diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 4028789..d80165e 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -29,6 +29,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -40,6 +42,10 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -72,6 +78,59 @@ iomux_v3_cfg_t usdhc4_pads[] = { MX6Q_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ }; +iomux_v3_cfg_t enet_pads1[] = { + MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* pin 35 - 1 (PHY_AD2) on reset */ + MX6Q_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 32 - 1 - (MODE0) all */ + MX6Q_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 31 - 1 - (MODE1) all */ + MX6Q_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 28 - 1 - (MODE2) all */ + MX6Q_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 27 - 1 - (MODE3) all */ + MX6Q_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ + MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 42 PHY nRST */ + MX6Q_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t enet_pads2[] = { + MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_enet(void) +{ + gpio_direction_output(87, 0); /* GPIO 3-23 */ + gpio_direction_output(190, 1); /* GPIO 6-30 */ + gpio_direction_output(185, 1); /* GPIO 6-25 */ + gpio_direction_output(187, 1); /* GPIO 6-27 */ + gpio_direction_output(188, 1); /* GPIO 6-28*/ + gpio_direction_output(189, 1); /* GPIO 6-29 */ + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); + gpio_direction_output(184, 1); /* GPIO 6-24 */ + + /* Need delay 10ms according to KSZ9021 spec */ + udelay(1000 * 10); + gpio_direction_output(87, 1); /* GPIO 3-23 */ + + imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); +} + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); @@ -128,6 +187,55 @@ int board_mmc_init(bd_t *bis) } #endif +#define MII_1000BASET_CTRL 0x9 +#define MII_EXTENDED_CTRL 0xb +#define MII_EXTENDED_DATAW 0xc + +int fecmxc_mii_postcall(int phy) +{ + /* prefer master mode */ + miiphy_write("FEC", phy, MII_1000BASET_CTRL, 0x0f00); + + /* min rx data delay */ + miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8105); + miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0x0000); + + /* max rx/tx clock delay, min rx/tx control delay */ + miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x8104); + miiphy_write("FEC", phy, MII_EXTENDED_DATAW, 0xf0f0); + miiphy_write("FEC", phy, MII_EXTENDED_CTRL, 0x104); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + struct eth_device *dev; + int ret; + + setup_iomux_enet(); + + ret = cpu_eth_init(bis); + if (ret) { + printf("FEC MXC: %s:failed\n", __func__); + return ret; + } + + dev = eth_get_dev_by_name("FEC"); + if (!dev) { + printf("FEC MXC: Unable to get FEC device entry\n"); + return -EINVAL; + } + + ret = fecmxc_register_mii_postcall(dev, fecmxc_mii_postcall); + if (ret) { + printf("FEC MXC: Unable to register FEC mii postcall\n"); + return ret; + } + + return 0; +} + int board_early_init_f(void) { setup_iomux_uart(); diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index 464f0ec..840e271 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -56,6 +56,17 @@ #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 6 + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 @@ -66,8 +77,6 @@ #include #undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS #define CONFIG_BOOTDELAY 3