Patchwork [U-Boot,2/3,v2] serial: add LPC32X0 high-speed UART devices support

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Submitter Vladimir Zapolskiy
Date Jan. 11, 2012, 11:12 p.m.
Message ID <1326323570-9394-3-git-send-email-vz@mleia.com>
Download mbox | patch
Permalink /patch/135529/
State Superseded
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Comments

Vladimir Zapolskiy - Jan. 11, 2012, 11:12 p.m.
This change adds an implementation of high-speed UART found on NXP
LPC32X0 SoCs. Such UARTs are enumerated as UART1, UART2 and UART7.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
---
Changes from v1 to v2:
* simplified lpc32xx_hsuart_init() a little
* put SoC specific changes into patch 1/3

 arch/arm/include/asm/arch-lpc32xx/uart.h |   60 ++++++++++++++++
 drivers/serial/Makefile                  |    1 +
 drivers/serial/lpc32xx_hsuart.c          |  112 ++++++++++++++++++++++++++++++
 3 files changed, 173 insertions(+), 0 deletions(-)
 create mode 100644 drivers/serial/lpc32xx_hsuart.c
Marek Vasut - Jan. 11, 2012, 11:52 p.m.
> This change adds an implementation of high-speed UART found on NXP
> LPC32X0 SoCs. Such UARTs are enumerated as UART1, UART2 and UART7.
> 
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
> Cc: Wolfgang Denk <wd@denx.de>
> ---
> Changes from v1 to v2:
> * simplified lpc32xx_hsuart_init() a little
> * put SoC specific changes into patch 1/3
> 
>  arch/arm/include/asm/arch-lpc32xx/uart.h |   60 ++++++++++++++++
>  drivers/serial/Makefile                  |    1 +
>  drivers/serial/lpc32xx_hsuart.c          |  112
> ++++++++++++++++++++++++++++++ 3 files changed, 173 insertions(+), 0
> deletions(-)
>  create mode 100644 drivers/serial/lpc32xx_hsuart.c
> 
> diff --git a/arch/arm/include/asm/arch-lpc32xx/uart.h
> b/arch/arm/include/asm/arch-lpc32xx/uart.h index 3c7e561..cb4853c 100644
> --- a/arch/arm/include/asm/arch-lpc32xx/uart.h
> +++ b/arch/arm/include/asm/arch-lpc32xx/uart.h
> @@ -22,6 +22,66 @@
> 
>  #include <asm/types.h>
> 
> +/* 14-clock UART Registers */
> +struct hsuart_t {
> +	union {
> +		u32 rx;		/* Receiver FIFO		*/
> +		u32 tx;		/* Transmitter FIFO		*/
> +	};
> +	u32 level;		/* FIFO Level Register		*/
> +	u32 iir;		/* Interrupt ID Register	*/
> +	u32 ctrl;		/* Control Register		*/
> +	u32 rate;		/* Rate Control Register	*/
> +};
> +
> +/* 14-clock UART Receiver FIFO Register bits */
> +#define HSUART_RX_BREAK			(1 << 10)
> +#define HSUART_RX_ERROR			(1 << 9)
> +#define HSUART_RX_EMPTY			(1 << 8)
> +#define HSUART_RX_DATA			(0xff << 0)
> +
> +/* 14-clock UART Level Register bits */
> +#define HSUART_LEVEL_TX			(0xff << 8)
> +#define HSUART_LEVEL_RX			(0xff << 0)
> +
> +/* 14-clock UART Interrupt Identification Register bits */
> +#define HSUART_IIR_TX_INT_SET		(1 << 6)
> +#define HSUART_IIR_RX_OE		(1 << 5)
> +#define HSUART_IIR_BRK			(1 << 4)
> +#define HSUART_IIR_FE			(1 << 3)
> +#define HSUART_IIR_RX_TIMEOUT		(1 << 2)
> +#define HSUART_IIR_RX_TRIG		(1 << 1)
> +#define HSUART_IIR_TX			(1 << 0)
> +
> +/* 14-clock UART Control Register bits */
> +#define HSUART_CTRL_HRTS_INV		(1 << 21)
> +#define HSUART_CTRL_HRTS_TRIG_48	(0x3 << 19)
> +#define HSUART_CTRL_HRTS_TRIG_32	(0x2 << 19)
> +#define HSUART_CTRL_HRTS_TRIG_16	(0x1 << 19)
> +#define HSUART_CTRL_HRTS_TRIG_8		(0x0 << 19)
> +#define HSUART_CTRL_HRTS_EN		(1 << 18)
> +#define HSUART_CTRL_TMO_16		(0x3 << 16)
> +#define HSUART_CTRL_TMO_8		(0x2 << 16)
> +#define HSUART_CTRL_TMO_4		(0x1 << 16)
> +#define HSUART_CTRL_TMO_DISABLED	(0x0 << 16)
> +#define HSUART_CTRL_HCTS_INV		(1 << 15)
> +#define HSUART_CTRL_HCTS_EN		(1 << 14)
> +#define HSUART_CTRL_HSU_OFFSET(n)	((n) << 9)
> +#define HSUART_CTRL_HSU_BREAK		(1 << 8)
> +#define HSUART_CTRL_HSU_ERR_INT_EN	(1 << 7)
> +#define HSUART_CTRL_HSU_RX_INT_EN	(1 << 6)
> +#define HSUART_CTRL_HSU_TX_INT_EN	(1 << 5)
> +#define HSUART_CTRL_HSU_RX_TRIG_48	(0x5 << 2)
> +#define HSUART_CTRL_HSU_RX_TRIG_32	(0x4 << 2)
> +#define HSUART_CTRL_HSU_RX_TRIG_16	(0x3 << 2)
> +#define HSUART_CTRL_HSU_RX_TRIG_8	(0x2 << 2)
> +#define HSUART_CTRL_HSU_RX_TRIG_4	(0x1 << 2)
> +#define HSUART_CTRL_HSU_RX_TRIG_1	(0x0 << 2)
> +#define HSUART_CTRL_HSU_TX_TRIG_16	(0x3 << 0)
> +#define HSUART_CTRL_HSU_TX_TRIG_8	(0x2 << 0)
> +#define HSUART_CTRL_HSU_TX_TRIG_4	(0x1 << 0)
> +#define HSUART_CTRL_HSU_TX_TRIG_0	(0x0 << 0)
> +
>  /* UART Control Registers */
>  struct uart_ctrl_t {
>  	u32 ctrl;		/* Control Register		*/
> diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
> index 616b857..65d0f23 100644
> --- a/drivers/serial/Makefile
> +++ b/drivers/serial/Makefile
> @@ -29,6 +29,7 @@ COBJS-$(CONFIG_ALTERA_UART) += altera_uart.o
>  COBJS-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
>  COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o
>  COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o
> +COBJS-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
>  COBJS-$(CONFIG_MCFUART) += mcfuart.o
>  COBJS-$(CONFIG_NS9750_UART) += ns9750_serial.o
>  COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
> diff --git a/drivers/serial/lpc32xx_hsuart.c
> b/drivers/serial/lpc32xx_hsuart.c new file mode 100644
> index 0000000..052b0d8
> --- /dev/null
> +++ b/drivers/serial/lpc32xx_hsuart.c
> @@ -0,0 +1,112 @@
> +/*
> + * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301, USA.
> + */
> +
> +#include <common.h>
> +#include <asm/arch/cpu.h>
> +#include <asm/arch/clk.h>
> +#include <asm/arch/uart.h>
> +#include <asm/io.h>

Is this uart compatible with any already in uboot ?

> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static struct hsuart_t *hsuart = (struct hsuart_t *)HS_UART_BASE;
> +
> +static void lpc32xx_hsuart_set_baudrate(void)
> +{
> +	u32 div;
> +
> +	/* UART rate = PERIPH_CLK / ((HSU_RATE + 1) × 14) */
> +	div = (get_serial_clock() / 14 + gd->baudrate / 2) / gd->baudrate - 1;
> +	if (div > 255)
> +		div = 255;
> +
> +	writel(div, &hsuart->rate);
> +}
> +
> +static int lpc32xx_hsuart_getc(void)
> +{
> +	while (!(readl(&hsuart->level) & HSUART_LEVEL_RX))
> +		/* NOP */;
> +
> +	return readl(&hsuart->rx) & HSUART_RX_DATA;
> +}
> +
> +static void lpc32xx_hsuart_putc(const char c)
> +{
> +	writel(c, &hsuart->tx);
> +
> +	/* Wait for character to be sent */
> +	while (readl(&hsuart->level) & HSUART_LEVEL_TX)
> +		/* NOP */;
> +}
> +
> +static int lpc32xx_hsuart_tstc(void)
> +{
> +	if (readl(&hsuart->level) & HSUART_LEVEL_RX)
> +		return 1;
> +
> +	return 0;
> +}
> +
> +static void lpc32xx_hsuart_init(void)
> +{
> +	lpc32xx_hsuart_set_baudrate();
> +
> +	/* Disable hardware RTS and CTS flow control, set up RX and TX FIFO */
> +	writel(HSUART_CTRL_TMO_16 | HSUART_CTRL_HSU_OFFSET(20) |
> +	       HSUART_CTRL_HSU_RX_TRIG_32 | HSUART_CTRL_HSU_TX_TRIG_0,
> +	       &hsuart->ctrl);
> +}
> +
> +void serial_setbrg(void)
> +{
> +	return lpc32xx_hsuart_set_baudrate();
> +}
> +
> +void serial_putc(const char c)
> +{
> +	lpc32xx_hsuart_putc(c);
> +
> +	/* If \n, also do \r */
> +	if (c == '\n')
> +		lpc32xx_hsuart_putc('\r');
> +}
> +
> +int serial_getc(void)
> +{
> +	return lpc32xx_hsuart_getc();
> +}
> +
> +void serial_puts(const char *s)
> +{
> +	while (*s)
> +		serial_putc(*s++);
> +}
> +
> +int serial_tstc(void)
> +{
> +	return lpc32xx_hsuart_tstc();
> +}
> +
> +int serial_init(void)
> +{
> +	lpc32xx_hsuart_init();
> +
> +	return 0;
> +}
Vladimir Zapolskiy - Jan. 12, 2012, 7:23 a.m.
On 12.01.2012 01:52, Marek Vasut wrote:
>> This change adds an implementation of high-speed UART found on NXP
>> LPC32X0 SoCs. Such UARTs are enumerated as UART1, UART2 and UART7.
>>
>> Signed-off-by: Vladimir Zapolskiy<vz@mleia.com>
>> Cc: Albert ARIBAUD<albert.u.boot@aribaud.net>
>> Cc: Wolfgang Denk<wd@denx.de>
>> ---
>> Changes from v1 to v2:
>> * simplified lpc32xx_hsuart_init() a little
>> * put SoC specific changes into patch 1/3
>>
>>   arch/arm/include/asm/arch-lpc32xx/uart.h |   60 ++++++++++++++++
>>   drivers/serial/Makefile                  |    1 +
>>   drivers/serial/lpc32xx_hsuart.c          |  112
>> ++++++++++++++++++++++++++++++ 3 files changed, 173 insertions(+), 0
>> deletions(-)
>>   create mode 100644 drivers/serial/lpc32xx_hsuart.c
>>
>> diff --git a/arch/arm/include/asm/arch-lpc32xx/uart.h
>> b/arch/arm/include/asm/arch-lpc32xx/uart.h index 3c7e561..cb4853c 100644
>> --- a/arch/arm/include/asm/arch-lpc32xx/uart.h
>> +++ b/arch/arm/include/asm/arch-lpc32xx/uart.h
>> @@ -22,6 +22,66 @@
>>
>>   #include<asm/types.h>
>>
>> +/* 14-clock UART Registers */
>> +struct hsuart_t {
>> +	union {
>> +		u32 rx;		/* Receiver FIFO		*/
>> +		u32 tx;		/* Transmitter FIFO		*/
>> +	};
>> +	u32 level;		/* FIFO Level Register		*/
>> +	u32 iir;		/* Interrupt ID Register	*/
>> +	u32 ctrl;		/* Control Register		*/
>> +	u32 rate;		/* Rate Control Register	*/
>> +};
>> +
>> +/* 14-clock UART Receiver FIFO Register bits */
>> +#define HSUART_RX_BREAK			(1<<  10)
>> +#define HSUART_RX_ERROR			(1<<  9)
>> +#define HSUART_RX_EMPTY			(1<<  8)
>> +#define HSUART_RX_DATA			(0xff<<  0)
>> +
>> +/* 14-clock UART Level Register bits */
>> +#define HSUART_LEVEL_TX			(0xff<<  8)
>> +#define HSUART_LEVEL_RX			(0xff<<  0)
>> +
>> +/* 14-clock UART Interrupt Identification Register bits */
>> +#define HSUART_IIR_TX_INT_SET		(1<<  6)
>> +#define HSUART_IIR_RX_OE		(1<<  5)
>> +#define HSUART_IIR_BRK			(1<<  4)
>> +#define HSUART_IIR_FE			(1<<  3)
>> +#define HSUART_IIR_RX_TIMEOUT		(1<<  2)
>> +#define HSUART_IIR_RX_TRIG		(1<<  1)
>> +#define HSUART_IIR_TX			(1<<  0)
>> +
>> +/* 14-clock UART Control Register bits */
>> +#define HSUART_CTRL_HRTS_INV		(1<<  21)
>> +#define HSUART_CTRL_HRTS_TRIG_48	(0x3<<  19)
>> +#define HSUART_CTRL_HRTS_TRIG_32	(0x2<<  19)
>> +#define HSUART_CTRL_HRTS_TRIG_16	(0x1<<  19)
>> +#define HSUART_CTRL_HRTS_TRIG_8		(0x0<<  19)
>> +#define HSUART_CTRL_HRTS_EN		(1<<  18)
>> +#define HSUART_CTRL_TMO_16		(0x3<<  16)
>> +#define HSUART_CTRL_TMO_8		(0x2<<  16)
>> +#define HSUART_CTRL_TMO_4		(0x1<<  16)
>> +#define HSUART_CTRL_TMO_DISABLED	(0x0<<  16)
>> +#define HSUART_CTRL_HCTS_INV		(1<<  15)
>> +#define HSUART_CTRL_HCTS_EN		(1<<  14)
>> +#define HSUART_CTRL_HSU_OFFSET(n)	((n)<<  9)
>> +#define HSUART_CTRL_HSU_BREAK		(1<<  8)
>> +#define HSUART_CTRL_HSU_ERR_INT_EN	(1<<  7)
>> +#define HSUART_CTRL_HSU_RX_INT_EN	(1<<  6)
>> +#define HSUART_CTRL_HSU_TX_INT_EN	(1<<  5)
>> +#define HSUART_CTRL_HSU_RX_TRIG_48	(0x5<<  2)
>> +#define HSUART_CTRL_HSU_RX_TRIG_32	(0x4<<  2)
>> +#define HSUART_CTRL_HSU_RX_TRIG_16	(0x3<<  2)
>> +#define HSUART_CTRL_HSU_RX_TRIG_8	(0x2<<  2)
>> +#define HSUART_CTRL_HSU_RX_TRIG_4	(0x1<<  2)
>> +#define HSUART_CTRL_HSU_RX_TRIG_1	(0x0<<  2)
>> +#define HSUART_CTRL_HSU_TX_TRIG_16	(0x3<<  0)
>> +#define HSUART_CTRL_HSU_TX_TRIG_8	(0x2<<  0)
>> +#define HSUART_CTRL_HSU_TX_TRIG_4	(0x1<<  0)
>> +#define HSUART_CTRL_HSU_TX_TRIG_0	(0x0<<  0)
>> +
>>   /* UART Control Registers */
>>   struct uart_ctrl_t {
>>   	u32 ctrl;		/* Control Register		*/
>> diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
>> index 616b857..65d0f23 100644
>> --- a/drivers/serial/Makefile
>> +++ b/drivers/serial/Makefile
>> @@ -29,6 +29,7 @@ COBJS-$(CONFIG_ALTERA_UART) += altera_uart.o
>>   COBJS-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
>>   COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o
>>   COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o
>> +COBJS-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
>>   COBJS-$(CONFIG_MCFUART) += mcfuart.o
>>   COBJS-$(CONFIG_NS9750_UART) += ns9750_serial.o
>>   COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
>> diff --git a/drivers/serial/lpc32xx_hsuart.c
>> b/drivers/serial/lpc32xx_hsuart.c new file mode 100644
>> index 0000000..052b0d8
>> --- /dev/null
>> +++ b/drivers/serial/lpc32xx_hsuart.c
>> @@ -0,0 +1,112 @@
>> +/*
>> + * Copyright (C) 2011 Vladimir Zapolskiy<vz@mleia.com>
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License
>> + * as published by the Free Software Foundation; either version 2
>> + * of the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
>> + * MA 02110-1301, USA.
>> + */
>> +
>> +#include<common.h>
>> +#include<asm/arch/cpu.h>
>> +#include<asm/arch/clk.h>
>> +#include<asm/arch/uart.h>
>> +#include<asm/io.h>
>
> Is this uart compatible with any already in uboot ?
>
IMHO it is not compatible with any other present in U-boot UART.

However there are 4 UARTS on the SoC, which are compatible with NS16550, 
but not this one.

>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +static struct hsuart_t *hsuart = (struct hsuart_t *)HS_UART_BASE;
>> +
>> +static void lpc32xx_hsuart_set_baudrate(void)
>> +{
>> +	u32 div;
>> +
>> +	/* UART rate = PERIPH_CLK / ((HSU_RATE + 1) × 14) */
>> +	div = (get_serial_clock() / 14 + gd->baudrate / 2) / gd->baudrate - 1;
>> +	if (div>  255)
>> +		div = 255;
>> +
>> +	writel(div,&hsuart->rate);
>> +}
>> +
>> +static int lpc32xx_hsuart_getc(void)
>> +{
>> +	while (!(readl(&hsuart->level)&  HSUART_LEVEL_RX))
>> +		/* NOP */;
>> +
>> +	return readl(&hsuart->rx)&  HSUART_RX_DATA;
>> +}
>> +
>> +static void lpc32xx_hsuart_putc(const char c)
>> +{
>> +	writel(c,&hsuart->tx);
>> +
>> +	/* Wait for character to be sent */
>> +	while (readl(&hsuart->level)&  HSUART_LEVEL_TX)
>> +		/* NOP */;
>> +}
>> +
>> +static int lpc32xx_hsuart_tstc(void)
>> +{
>> +	if (readl(&hsuart->level)&  HSUART_LEVEL_RX)
>> +		return 1;
>> +
>> +	return 0;
>> +}
>> +
>> +static void lpc32xx_hsuart_init(void)
>> +{
>> +	lpc32xx_hsuart_set_baudrate();
>> +
>> +	/* Disable hardware RTS and CTS flow control, set up RX and TX FIFO */
>> +	writel(HSUART_CTRL_TMO_16 | HSUART_CTRL_HSU_OFFSET(20) |
>> +	       HSUART_CTRL_HSU_RX_TRIG_32 | HSUART_CTRL_HSU_TX_TRIG_0,
>> +	&hsuart->ctrl);
>> +}
>> +
>> +void serial_setbrg(void)
>> +{
>> +	return lpc32xx_hsuart_set_baudrate();
>> +}
>> +
>> +void serial_putc(const char c)
>> +{
>> +	lpc32xx_hsuart_putc(c);
>> +
>> +	/* If \n, also do \r */
>> +	if (c == '\n')
>> +		lpc32xx_hsuart_putc('\r');
>> +}
>> +
>> +int serial_getc(void)
>> +{
>> +	return lpc32xx_hsuart_getc();
>> +}
>> +
>> +void serial_puts(const char *s)
>> +{
>> +	while (*s)
>> +		serial_putc(*s++);
>> +}
>> +
>> +int serial_tstc(void)
>> +{
>> +	return lpc32xx_hsuart_tstc();
>> +}
>> +
>> +int serial_init(void)
>> +{
>> +	lpc32xx_hsuart_init();
>> +
>> +	return 0;
>> +}

Patch

diff --git a/arch/arm/include/asm/arch-lpc32xx/uart.h b/arch/arm/include/asm/arch-lpc32xx/uart.h
index 3c7e561..cb4853c 100644
--- a/arch/arm/include/asm/arch-lpc32xx/uart.h
+++ b/arch/arm/include/asm/arch-lpc32xx/uart.h
@@ -22,6 +22,66 @@ 
 
 #include <asm/types.h>
 
+/* 14-clock UART Registers */
+struct hsuart_t {
+	union {
+		u32 rx;		/* Receiver FIFO		*/
+		u32 tx;		/* Transmitter FIFO		*/
+	};
+	u32 level;		/* FIFO Level Register		*/
+	u32 iir;		/* Interrupt ID Register	*/
+	u32 ctrl;		/* Control Register		*/
+	u32 rate;		/* Rate Control Register	*/
+};
+
+/* 14-clock UART Receiver FIFO Register bits */
+#define HSUART_RX_BREAK			(1 << 10)
+#define HSUART_RX_ERROR			(1 << 9)
+#define HSUART_RX_EMPTY			(1 << 8)
+#define HSUART_RX_DATA			(0xff << 0)
+
+/* 14-clock UART Level Register bits */
+#define HSUART_LEVEL_TX			(0xff << 8)
+#define HSUART_LEVEL_RX			(0xff << 0)
+
+/* 14-clock UART Interrupt Identification Register bits */
+#define HSUART_IIR_TX_INT_SET		(1 << 6)
+#define HSUART_IIR_RX_OE		(1 << 5)
+#define HSUART_IIR_BRK			(1 << 4)
+#define HSUART_IIR_FE			(1 << 3)
+#define HSUART_IIR_RX_TIMEOUT		(1 << 2)
+#define HSUART_IIR_RX_TRIG		(1 << 1)
+#define HSUART_IIR_TX			(1 << 0)
+
+/* 14-clock UART Control Register bits */
+#define HSUART_CTRL_HRTS_INV		(1 << 21)
+#define HSUART_CTRL_HRTS_TRIG_48	(0x3 << 19)
+#define HSUART_CTRL_HRTS_TRIG_32	(0x2 << 19)
+#define HSUART_CTRL_HRTS_TRIG_16	(0x1 << 19)
+#define HSUART_CTRL_HRTS_TRIG_8		(0x0 << 19)
+#define HSUART_CTRL_HRTS_EN		(1 << 18)
+#define HSUART_CTRL_TMO_16		(0x3 << 16)
+#define HSUART_CTRL_TMO_8		(0x2 << 16)
+#define HSUART_CTRL_TMO_4		(0x1 << 16)
+#define HSUART_CTRL_TMO_DISABLED	(0x0 << 16)
+#define HSUART_CTRL_HCTS_INV		(1 << 15)
+#define HSUART_CTRL_HCTS_EN		(1 << 14)
+#define HSUART_CTRL_HSU_OFFSET(n)	((n) << 9)
+#define HSUART_CTRL_HSU_BREAK		(1 << 8)
+#define HSUART_CTRL_HSU_ERR_INT_EN	(1 << 7)
+#define HSUART_CTRL_HSU_RX_INT_EN	(1 << 6)
+#define HSUART_CTRL_HSU_TX_INT_EN	(1 << 5)
+#define HSUART_CTRL_HSU_RX_TRIG_48	(0x5 << 2)
+#define HSUART_CTRL_HSU_RX_TRIG_32	(0x4 << 2)
+#define HSUART_CTRL_HSU_RX_TRIG_16	(0x3 << 2)
+#define HSUART_CTRL_HSU_RX_TRIG_8	(0x2 << 2)
+#define HSUART_CTRL_HSU_RX_TRIG_4	(0x1 << 2)
+#define HSUART_CTRL_HSU_RX_TRIG_1	(0x0 << 2)
+#define HSUART_CTRL_HSU_TX_TRIG_16	(0x3 << 0)
+#define HSUART_CTRL_HSU_TX_TRIG_8	(0x2 << 0)
+#define HSUART_CTRL_HSU_TX_TRIG_4	(0x1 << 0)
+#define HSUART_CTRL_HSU_TX_TRIG_0	(0x0 << 0)
+
 /* UART Control Registers */
 struct uart_ctrl_t {
 	u32 ctrl;		/* Control Register		*/
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 616b857..65d0f23 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -29,6 +29,7 @@  COBJS-$(CONFIG_ALTERA_UART) += altera_uart.o
 COBJS-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
 COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o
 COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o
+COBJS-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
 COBJS-$(CONFIG_MCFUART) += mcfuart.o
 COBJS-$(CONFIG_NS9750_UART) += ns9750_serial.o
 COBJS-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o
diff --git a/drivers/serial/lpc32xx_hsuart.c b/drivers/serial/lpc32xx_hsuart.c
new file mode 100644
index 0000000..052b0d8
--- /dev/null
+++ b/drivers/serial/lpc32xx_hsuart.c
@@ -0,0 +1,112 @@ 
+/*
+ * Copyright (C) 2011 Vladimir Zapolskiy <vz@mleia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/uart.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static struct hsuart_t *hsuart = (struct hsuart_t *)HS_UART_BASE;
+
+static void lpc32xx_hsuart_set_baudrate(void)
+{
+	u32 div;
+
+	/* UART rate = PERIPH_CLK / ((HSU_RATE + 1) × 14) */
+	div = (get_serial_clock() / 14 + gd->baudrate / 2) / gd->baudrate - 1;
+	if (div > 255)
+		div = 255;
+
+	writel(div, &hsuart->rate);
+}
+
+static int lpc32xx_hsuart_getc(void)
+{
+	while (!(readl(&hsuart->level) & HSUART_LEVEL_RX))
+		/* NOP */;
+
+	return readl(&hsuart->rx) & HSUART_RX_DATA;
+}
+
+static void lpc32xx_hsuart_putc(const char c)
+{
+	writel(c, &hsuart->tx);
+
+	/* Wait for character to be sent */
+	while (readl(&hsuart->level) & HSUART_LEVEL_TX)
+		/* NOP */;
+}
+
+static int lpc32xx_hsuart_tstc(void)
+{
+	if (readl(&hsuart->level) & HSUART_LEVEL_RX)
+		return 1;
+
+	return 0;
+}
+
+static void lpc32xx_hsuart_init(void)
+{
+	lpc32xx_hsuart_set_baudrate();
+
+	/* Disable hardware RTS and CTS flow control, set up RX and TX FIFO */
+	writel(HSUART_CTRL_TMO_16 | HSUART_CTRL_HSU_OFFSET(20) |
+	       HSUART_CTRL_HSU_RX_TRIG_32 | HSUART_CTRL_HSU_TX_TRIG_0,
+	       &hsuart->ctrl);
+}
+
+void serial_setbrg(void)
+{
+	return lpc32xx_hsuart_set_baudrate();
+}
+
+void serial_putc(const char c)
+{
+	lpc32xx_hsuart_putc(c);
+
+	/* If \n, also do \r */
+	if (c == '\n')
+		lpc32xx_hsuart_putc('\r');
+}
+
+int serial_getc(void)
+{
+	return lpc32xx_hsuart_getc();
+}
+
+void serial_puts(const char *s)
+{
+	while (*s)
+		serial_putc(*s++);
+}
+
+int serial_tstc(void)
+{
+	return lpc32xx_hsuart_tstc();
+}
+
+int serial_init(void)
+{
+	lpc32xx_hsuart_init();
+
+	return 0;
+}