From patchwork Wed Jan 11 23:12:52 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 135527 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 32A27B6EF7 for ; Thu, 12 Jan 2012 10:13:07 +1100 (EST) Received: from localhost ([::1]:41656 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rl7Lt-0001GU-C6 for incoming@patchwork.ozlabs.org; Wed, 11 Jan 2012 18:13:05 -0500 Received: from eggs.gnu.org ([140.186.70.92]:55845) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rl7Lk-0001G8-JI for qemu-devel@nongnu.org; Wed, 11 Jan 2012 18:13:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rl7Li-0003Jd-OO for qemu-devel@nongnu.org; Wed, 11 Jan 2012 18:12:56 -0500 Received: from cantor2.suse.de ([195.135.220.15]:59038 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rl7Li-0003JL-GW; Wed, 11 Jan 2012 18:12:54 -0500 Received: from relay1.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 1561189994; Thu, 12 Jan 2012 00:12:53 +0100 (CET) From: Alexander Graf To: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 12 Jan 2012 00:12:52 +0100 Message-Id: <1326323572-21401-1-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <4F0E026B.6010400@suse.de> References: <4F0E026B.6010400@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: qemu-ppc@nongnu.org, "qemu-devel@nongnu.org Developers" , Avi Kivity Subject: [Qemu-devel] [PATCH] PREP: Finish qdev conversion X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org In your previous 2 patches you start off with a really nice qdev conversion, don't finish it unfortunately though. This patch goes the final mile and does what's necessary to address the comments I had. Signed-off-by: Alexander Graf --- hw/ppc_prep.c | 14 ++++++++++- hw/prep_pci.c | 72 +++++++++++++++++++++++++++----------------------------- 2 files changed, 48 insertions(+), 38 deletions(-) diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c index dec059a..af80e43 100644 --- a/hw/ppc_prep.c +++ b/hw/ppc_prep.c @@ -39,6 +39,7 @@ #include "mc146818rtc.h" #include "blockdev.h" #include "exec-memory.h" +#include "sysbus.h" //#define HARD_DEBUG_PPC_IO //#define DEBUG_PPC_IO @@ -529,6 +530,7 @@ static void ppc_prep_init (ram_addr_t ram_size, int ppc_boot_device; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; DriveInfo *fd[MAX_FD]; + DeviceState *dev; sysctrl = g_malloc0(sizeof(sysctrl_t)); @@ -633,7 +635,17 @@ static void ppc_prep_init (ram_addr_t ram_size, /* Hmm, prep has no pci-isa bridge ??? */ isa_bus = isa_bus_new(NULL, get_system_io()); i8259 = i8259_init(isa_bus, first_cpu->irq_inputs[PPC6xx_INPUT_INT]); - pci_bus = pci_prep_init(i8259, get_system_memory(), get_system_io()); + + dev = qdev_create(NULL, "raven-pcihost"); + dev = sysbus_create_varargs("raven-pcihost", 0x80800000, + i8259[9], i8259[11], i8259[9], i8259[11], + NULL); + pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); + if (!pci_bus) { + fprintf(stderr, "couldn't create PCI controller!\n"); + exit(1); + } + isa_bus_irqs(isa_bus, i8259); // pci_bus = i440fx_init(); /* Register 8 MB of ISA IO space (needed for non-contiguous map) */ diff --git a/hw/prep_pci.c b/hw/prep_pci.c index 2ff6b8c..015f029 100644 --- a/hw/prep_pci.c +++ b/hw/prep_pci.c @@ -26,8 +26,12 @@ #include "pci.h" #include "pci_host.h" #include "prep_pci.h" +#include "exec-memory.h" -typedef PCIHostState PREPPCIState; +typedef struct PREPPCIState { + PCIHostState pci_state; + qemu_irq irq[4]; +} PREPPCIState; typedef struct RavenPCIState { PCIDevice dev; @@ -47,28 +51,28 @@ static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr) static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val) { PREPPCIState *s = opaque; - pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 1); + pci_data_write(s->pci_state.bus, PPC_PCIIO_config(addr), val, 1); } static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val) { PREPPCIState *s = opaque; val = bswap16(val); - pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2); + pci_data_write(s->pci_state.bus, PPC_PCIIO_config(addr), val, 2); } static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val) { PREPPCIState *s = opaque; val = bswap32(val); - pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4); + pci_data_write(s->pci_state.bus, PPC_PCIIO_config(addr), val, 4); } static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr) { PREPPCIState *s = opaque; uint32_t val; - val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 1); + val = pci_data_read(s->pci_state.bus, PPC_PCIIO_config(addr), 1); return val; } @@ -76,7 +80,7 @@ static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr) { PREPPCIState *s = opaque; uint32_t val; - val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 2); + val = pci_data_read(s->pci_state.bus, PPC_PCIIO_config(addr), 2); val = bswap16(val); return val; } @@ -85,7 +89,7 @@ static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr) { PREPPCIState *s = opaque; uint32_t val; - val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4); + val = pci_data_read(s->pci_state.bus, PPC_PCIIO_config(addr), 4); val = bswap32(val); return val; } @@ -106,49 +110,43 @@ static int prep_map_irq(PCIDevice *pci_dev, int irq_num) static void prep_set_irq(void *opaque, int irq_num, int level) { qemu_irq *pic = opaque; - - qemu_set_irq(pic[(irq_num & 1) ? 11 : 9] , level); + qemu_set_irq(pic[irq_num], level); } -PCIBus *pci_prep_init(qemu_irq *pic, - MemoryRegion *address_space_mem, - MemoryRegion *address_space_io) +static int raven_pcihost_init(SysBusDevice *dev) { - DeviceState *dev; + PCIHostState *h; PREPPCIState *s; + MemoryRegion *address_space_mem = get_system_memory(); + MemoryRegion *address_space_io = get_system_io(); + int i; + + h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev)); + s = DO_UPCAST(PREPPCIState, pci_state, h); + + for (i = 0; i < ARRAY_SIZE(s->irq); i++) { + sysbus_init_irq(dev, &s->irq[i]); + } - dev = qdev_create(NULL, "raven-pcihost"); - s = FROM_SYSBUS(PREPPCIState, sysbus_from_qdev(dev)); - s->address_space = address_space_mem; - s->bus = pci_register_bus(&s->busdev.qdev, "pci", - prep_set_irq, prep_map_irq, pic, + h->bus = pci_register_bus(&h->busdev.qdev, NULL, + prep_set_irq, prep_map_irq, s->irq, address_space_mem, address_space_io, 0, 4); - qdev_init_nofail(dev); - qdev_property_add_child(qdev_get_root(), "raven", dev, NULL); + pci_create_simple(h->bus, 0, "raven"); - memory_region_init_io(&s->mmcfg, &PPC_PCIIO_ops, s, "pciio", 0x00400000); - memory_region_add_subregion(address_space_mem, 0x80800000, &s->mmcfg); - - pci_create_simple(s->bus, 0, "raven"); - - return s->bus; -} - -static int raven_pcihost_init(SysBusDevice *dev) -{ - PREPPCIState *s = FROM_SYSBUS(PREPPCIState, dev); + memory_region_init_io(&h->mmcfg, &PPC_PCIIO_ops, s, "pciio", 0x00400000); + sysbus_init_mmio(dev, &h->mmcfg); - memory_region_init_io(&s->conf_mem, &pci_host_conf_be_ops, s, + memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, s, "pci-conf-idx", 1); - sysbus_add_io(dev, 0xcf8, &s->conf_mem); - sysbus_init_ioports(&s->busdev, 0xcf8, 1); + sysbus_add_io(dev, 0xcf8, &h->conf_mem); + sysbus_init_ioports(&h->busdev, 0xcf8, 1); - memory_region_init_io(&s->data_mem, &pci_host_data_be_ops, s, + memory_region_init_io(&h->data_mem, &pci_host_data_be_ops, s, "pci-conf-data", 1); - sysbus_add_io(dev, 0xcfc, &s->data_mem); - sysbus_init_ioports(&s->busdev, 0xcfc, 1); + sysbus_add_io(dev, 0xcfc, &h->data_mem); + sysbus_init_ioports(&h->busdev, 0xcfc, 1); return 0; }