From patchwork Tue Jan 10 19:44:23 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 135301 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id AB697B6FC8 for ; Wed, 11 Jan 2012 06:43:15 +1100 (EST) Received: from localhost ([::1]:41567 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RkhbB-0005qa-Qg for incoming@patchwork.ozlabs.org; Tue, 10 Jan 2012 14:43:09 -0500 Received: from eggs.gnu.org ([140.186.70.92]:36582) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rkhb1-0005pt-1R for qemu-devel@nongnu.org; Tue, 10 Jan 2012 14:43:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rkhaz-0003YU-61 for qemu-devel@nongnu.org; Tue, 10 Jan 2012 14:42:59 -0500 Received: from cantor2.suse.de ([195.135.220.15]:44644 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rkhay-0003YH-JO; Tue, 10 Jan 2012 14:42:57 -0500 Received: from relay2.suse.de (unknown [195.135.220.254]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 6A96F95EF2; Tue, 10 Jan 2012 20:42:55 +0100 (CET) From: Alexander Graf To: "qemu-devel@nongnu.org Developers" Date: Tue, 10 Jan 2012 20:44:23 +0100 Message-Id: <1326224664-30272-5-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1326224664-30272-1-git-send-email-agraf@suse.de> References: <1326224664-30272-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.15 Cc: qemu-ppc@nongnu.org Subject: [Qemu-devel] [PATCH 4/5] PPC: Bamboo: fold ppc440.c and ppc440_bamboo.c into a single file X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The separation of ppc440 and ppc440_bamboo makes some sense, since ppc440 is the SoC while ppc440_bamboo is the actual board. But the separation makes things harder for us for no good reason, so let's just fold them in together with each other. Signed-off-by: Alexander Graf --- Makefile.target | 2 +- hw/ppc440.c | 107 ---------------------------------------------------- hw/ppc440.h | 21 ---------- hw/ppc440_bamboo.c | 90 +++++++++++++++++++++++++++++++++++++++++++- hw/virtex_ml507.c | 1 - 5 files changed, 90 insertions(+), 131 deletions(-) delete mode 100644 hw/ppc440.c delete mode 100644 hw/ppc440.h diff --git a/Makefile.target b/Makefile.target index 06d79b8..a67e1fe 100644 --- a/Makefile.target +++ b/Makefile.target @@ -250,7 +250,7 @@ obj-ppc-$(CONFIG_PSERIES) += xics.o spapr_vty.o spapr_llan.o spapr_vscsi.o obj-ppc-$(CONFIG_PSERIES) += spapr_pci.o device-hotplug.o pci-hotplug.o # PowerPC 4xx boards obj-ppc-y += ppc4xx_devs.o ppc4xx_pci.o ppc405_uc.o ppc405_boards.o -obj-ppc-y += ppc440.o ppc440_bamboo.o +obj-ppc-y += ppc440_bamboo.o # PowerPC E500 boards obj-ppc-y += ppce500_mpc8544ds.o mpc8544_guts.o ppce500_spin.o # PowerPC 440 Xilinx ML507 reference board. diff --git a/hw/ppc440.c b/hw/ppc440.c deleted file mode 100644 index 8920abb..0000000 --- a/hw/ppc440.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Qemu PowerPC 440 chip emulation - * - * Copyright 2007 IBM Corporation. - * Authors: - * Jerone Young - * Christian Ehrhardt - * Hollis Blanchard - * - * This work is licensed under the GNU GPL license version 2 or later. - * - */ - -#include "hw.h" -#include "pc.h" -#include "isa.h" -#include "ppc.h" -#include "ppc4xx.h" -#include "ppc440.h" -#include "ppc405.h" -#include "sysemu.h" -#include "kvm.h" - -#define PPC440EP_PCI_CONFIG 0xeec00000 -#define PPC440EP_PCI_INTACK 0xeed00000 -#define PPC440EP_PCI_SPECIAL 0xeed00000 -#define PPC440EP_PCI_REGS 0xef400000 -#define PPC440EP_PCI_IO 0xe8000000 -#define PPC440EP_PCI_IOLEN 0x00010000 - -#define PPC440EP_SDRAM_NR_BANKS 4 - -static const unsigned int ppc440ep_sdram_bank_sizes[] = { - 256<<20, 128<<20, 64<<20, 32<<20, 16<<20, 8<<20, 0 -}; - -CPUState *ppc440ep_init(MemoryRegion *address_space_mem, ram_addr_t *ram_size, - PCIBus **pcip, const unsigned int pci_irq_nrs[4], - int do_init, const char *cpu_model) -{ - MemoryRegion *ram_memories - = g_malloc(PPC440EP_SDRAM_NR_BANKS * sizeof(*ram_memories)); - target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS]; - target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS]; - CPUState *env; - qemu_irq *pic; - qemu_irq *irqs; - qemu_irq *pci_irqs; - - if (cpu_model == NULL) { - cpu_model = "440EP"; - } - env = cpu_init(cpu_model); - if (!env) { - fprintf(stderr, "Unable to initialize CPU!\n"); - exit(1); - } - - ppc_booke_timers_init(env, 400000000, 0); - ppc_dcr_init(env, NULL, NULL); - - /* interrupt controller */ - irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB); - irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; - irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; - pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); - - /* SDRAM controller */ - memset(ram_bases, 0, sizeof(ram_bases)); - memset(ram_sizes, 0, sizeof(ram_sizes)); - *ram_size = ppc4xx_sdram_adjust(*ram_size, PPC440EP_SDRAM_NR_BANKS, - ram_memories, - ram_bases, ram_sizes, - ppc440ep_sdram_bank_sizes); - /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */ - ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories, - ram_bases, ram_sizes, do_init); - - /* PCI */ - pci_irqs = g_malloc(sizeof(qemu_irq) * 4); - pci_irqs[0] = pic[pci_irq_nrs[0]]; - pci_irqs[1] = pic[pci_irq_nrs[1]]; - pci_irqs[2] = pic[pci_irq_nrs[2]]; - pci_irqs[3] = pic[pci_irq_nrs[3]]; - *pcip = ppc4xx_pci_init(env, pci_irqs, - PPC440EP_PCI_CONFIG, - PPC440EP_PCI_INTACK, - PPC440EP_PCI_SPECIAL, - PPC440EP_PCI_REGS); - if (!*pcip) - printf("couldn't create PCI controller!\n"); - - isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN); - - if (serial_hds[0] != NULL) { - serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], - PPC_SERIAL_MM_BAUDBASE, serial_hds[0], - DEVICE_BIG_ENDIAN); - } - if (serial_hds[1] != NULL) { - serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], - PPC_SERIAL_MM_BAUDBASE, serial_hds[1], - DEVICE_BIG_ENDIAN); - } - - return env; -} diff --git a/hw/ppc440.h b/hw/ppc440.h deleted file mode 100644 index 9c27c36..0000000 --- a/hw/ppc440.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Qemu PowerPC 440 board emualtion - * - * Copyright 2007 IBM Corporation. - * Authors: Jerone Young - * Christian Ehrhardt - * - * This work is licensed under the GNU GPL licence version 2 or later - * - */ - -#ifndef QEMU_PPC440_H -#define QEMU_PPC440_H - -#include "hw.h" - -CPUState *ppc440ep_init(MemoryRegion *address_space, ram_addr_t *ram_size, - PCIBus **pcip, const unsigned int pci_irq_nrs[4], - int do_init, const char *cpu_model); - -#endif diff --git a/hw/ppc440_bamboo.c b/hw/ppc440_bamboo.c index 124e7d7..d00bdda 100644 --- a/hw/ppc440_bamboo.c +++ b/hw/ppc440_bamboo.c @@ -17,13 +17,16 @@ #include "hw.h" #include "pci.h" #include "boards.h" -#include "ppc440.h" #include "kvm.h" #include "kvm_ppc.h" #include "device_tree.h" #include "loader.h" #include "elf.h" #include "exec-memory.h" +#include "pc.h" +#include "ppc.h" +#include "ppc405.h" +#include "sysemu.h" #define BINARY_DEVICE_TREE_FILE "bamboo.dtb" @@ -32,6 +35,19 @@ #define FDT_ADDR 0x1800000 #define RAMDISK_ADDR 0x1900000 +#define PPC440EP_PCI_CONFIG 0xeec00000 +#define PPC440EP_PCI_INTACK 0xeed00000 +#define PPC440EP_PCI_SPECIAL 0xeed00000 +#define PPC440EP_PCI_REGS 0xef400000 +#define PPC440EP_PCI_IO 0xe8000000 +#define PPC440EP_PCI_IOLEN 0x00010000 + +#define PPC440EP_SDRAM_NR_BANKS 4 + +static const unsigned int ppc440ep_sdram_bank_sizes[] = { + 256<<20, 128<<20, 64<<20, 32<<20, 16<<20, 8<<20, 0 +}; + static target_phys_addr_t entry; static PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4], @@ -43,6 +59,78 @@ static PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4], return NULL; } +CPUState *ppc440ep_init(MemoryRegion *address_space_mem, ram_addr_t *ram_size, + PCIBus **pcip, const unsigned int pci_irq_nrs[4], + int do_init, const char *cpu_model) +{ + MemoryRegion *ram_memories + = g_malloc(PPC440EP_SDRAM_NR_BANKS * sizeof(*ram_memories)); + target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS]; + target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS]; + CPUState *env; + qemu_irq *pic; + qemu_irq *irqs; + qemu_irq *pci_irqs; + + if (cpu_model == NULL) { + cpu_model = "440EP"; + } + env = cpu_init(cpu_model); + if (!env) { + fprintf(stderr, "Unable to initialize CPU!\n"); + exit(1); + } + + ppc_booke_timers_init(env, 400000000, 0); + ppc_dcr_init(env, NULL, NULL); + + /* interrupt controller */ + irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB); + irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; + irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; + pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); + + /* SDRAM controller */ + memset(ram_bases, 0, sizeof(ram_bases)); + memset(ram_sizes, 0, sizeof(ram_sizes)); + *ram_size = ppc4xx_sdram_adjust(*ram_size, PPC440EP_SDRAM_NR_BANKS, + ram_memories, + ram_bases, ram_sizes, + ppc440ep_sdram_bank_sizes); + /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */ + ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories, + ram_bases, ram_sizes, do_init); + + /* PCI */ + pci_irqs = g_malloc(sizeof(qemu_irq) * 4); + pci_irqs[0] = pic[pci_irq_nrs[0]]; + pci_irqs[1] = pic[pci_irq_nrs[1]]; + pci_irqs[2] = pic[pci_irq_nrs[2]]; + pci_irqs[3] = pic[pci_irq_nrs[3]]; + *pcip = ppc4xx_pci_init(env, pci_irqs, + PPC440EP_PCI_CONFIG, + PPC440EP_PCI_INTACK, + PPC440EP_PCI_SPECIAL, + PPC440EP_PCI_REGS); + if (!*pcip) + printf("couldn't create PCI controller!\n"); + + isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN); + + if (serial_hds[0] != NULL) { + serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], + PPC_SERIAL_MM_BAUDBASE, serial_hds[0], + DEVICE_BIG_ENDIAN); + } + if (serial_hds[1] != NULL) { + serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], + PPC_SERIAL_MM_BAUDBASE, serial_hds[1], + DEVICE_BIG_ENDIAN); + } + + return env; +} + static int bamboo_load_device_tree(target_phys_addr_t addr, uint32_t ramsize, target_phys_addr_t initrd_base, diff --git a/hw/virtex_ml507.c b/hw/virtex_ml507.c index bd16b97..f8d2b1b 100644 --- a/hw/virtex_ml507.c +++ b/hw/virtex_ml507.c @@ -38,7 +38,6 @@ #include "ppc.h" #include "ppc4xx.h" -#include "ppc440.h" #include "ppc405.h" #include "blockdev.h"