From patchwork Tue Jan 10 10:27:25 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Edgar E. Iglesias" X-Patchwork-Id: 135255 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D1335B6FB6 for ; Wed, 11 Jan 2012 02:35:03 +1100 (EST) Received: from localhost ([::1]:57924 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rkczr-0006SD-QZ for incoming@patchwork.ozlabs.org; Tue, 10 Jan 2012 09:48:19 -0500 Received: from eggs.gnu.org ([140.186.70.92]:34324) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RkYve-0003TQ-DJ for qemu-devel@nongnu.org; Tue, 10 Jan 2012 05:27:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RkYvX-0004js-Ti for qemu-devel@nongnu.org; Tue, 10 Jan 2012 05:27:42 -0500 Received: from anubis.se.axis.com ([195.60.68.12]:38814) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RkYvX-0004ij-Hb for qemu-devel@nongnu.org; Tue, 10 Jan 2012 05:27:35 -0500 Received: from localhost (localhost [127.0.0.1]) by anubis.se.axis.com (Postfix) with ESMTP id 8A04E19DCF for ; Tue, 10 Jan 2012 11:27:29 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at anubis.se.axis.com X-Amavis-Alert: BAD HEADER SECTION, Duplicate header field: "To" Received: from anubis.se.axis.com ([127.0.0.1]) by localhost (anubis.se.axis.com [127.0.0.1]) (amavisd-new, port 10024) with LMTP id vGwdOe60CyXS for ; Tue, 10 Jan 2012 11:27:28 +0100 (CET) Received: from thoth.se.axis.com (thoth.se.axis.com [10.0.2.173]) by anubis.se.axis.com (Postfix) with ESMTP id A6E3E19E03 for ; Tue, 10 Jan 2012 11:27:27 +0100 (CET) Received: from localhost (edgar.se.axis.com [10.93.151.1]) by thoth.se.axis.com (Postfix) with ESMTP id 820BA34102 for ; Tue, 10 Jan 2012 11:27:27 +0100 (CET) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Date: Tue, 10 Jan 2012 11:27:25 +0100 Message-Id: <1326191247-14880-2-git-send-email-edgar.iglesias@gmail.com> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1326191247-14880-1-git-send-email-edgar.iglesias@gmail.com> References: <1326191247-14880-1-git-send-email-edgar.iglesias@gmail.com> To: edgar.iglesias@gmail.com X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 195.60.68.12 X-Mailman-Approved-At: Tue, 10 Jan 2012 09:47:50 -0500 Subject: [Qemu-devel] [PATCH] microblaze: Emulate the hw stackprotector X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Edgar E. Iglesias --- target-microblaze/cpu.h | 3 +++ target-microblaze/helper.h | 1 + target-microblaze/op_helper.c | 11 +++++++++++ target-microblaze/translate.c | 33 +++++++++++++++++++++++++++++++++ 4 files changed, 48 insertions(+), 0 deletions(-) diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index 1a307e3..3ecaeee 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -93,6 +93,7 @@ struct CPUMBState; #define ESR_EC_DIVZERO 5 #define ESR_EC_FPU 6 #define ESR_EC_PRIVINSN 7 +#define ESR_EC_STACKPROT 7 /* Same as PRIVINSN. */ #define ESR_EC_DATA_STORAGE 8 #define ESR_EC_INSN_STORAGE 9 #define ESR_EC_DATA_TLB 10 @@ -235,6 +236,8 @@ typedef struct CPUMBState { uint32_t regs[33]; uint32_t sregs[24]; float_status fp_status; + /* Stack protectors. Yes, it's a hw feature. */ + uint32_t slr, shr; /* Internal flags. */ #define IMM_FLAG 4 diff --git a/target-microblaze/helper.h b/target-microblaze/helper.h index 420ff3b..2205d5a 100644 --- a/target-microblaze/helper.h +++ b/target-microblaze/helper.h @@ -33,6 +33,7 @@ DEF_HELPER_2(mmu_write, void, i32, i32) #endif DEF_HELPER_4(memalign, void, i32, i32, i32, i32) +DEF_HELPER_1(stackprot, void, i32) DEF_HELPER_2(get, i32, i32, i32) DEF_HELPER_3(put, void, i32, i32, i32) diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c index fe38b7b..5fd7906 100644 --- a/target-microblaze/op_helper.c +++ b/target-microblaze/op_helper.c @@ -489,6 +489,17 @@ void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask) } } +void helper_stackprot(uint32_t addr) +{ + if (addr < env->slr || addr > env->shr) { + qemu_log("Stack protector violation at %x %x %x\n", + addr, env->slr, env->shr); + env->sregs[SR_EAR] = addr; + env->sregs[SR_ESR] = ESR_EC_STACKPROT; + helper_raise_exception(EXCP_HW_EXCP); + } +} + #if !defined(CONFIG_USER_ONLY) /* Writes/reads to the MMU's special regs end up here. */ uint32_t helper_mmu_read(uint32_t rn) diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index f4e6f30..180ac84 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -526,6 +526,12 @@ static void dec_msr(DisasContext *dc) case 0x7: tcg_gen_andi_tl(cpu_SR[SR_FSR], cpu_R[dc->ra], 31); break; + case 0x800: + tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUState, slr)); + break; + case 0x802: + tcg_gen_st_tl(cpu_R[dc->ra], cpu_env, offsetof(CPUState, shr)); + break; default: cpu_abort(dc->env, "unknown mts reg %x\n", sr); break; @@ -552,6 +558,12 @@ static void dec_msr(DisasContext *dc) case 0xb: tcg_gen_mov_tl(cpu_R[dc->rd], cpu_SR[SR_BTR]); break; + case 0x800: + tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUState, slr)); + break; + case 0x802: + tcg_gen_ld_tl(cpu_R[dc->rd], cpu_env, offsetof(CPUState, shr)); + break; case 0x2000: case 0x2001: case 0x2002: @@ -864,6 +876,13 @@ static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr, static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t) { unsigned int extimm = dc->tb_flags & IMM_FLAG; + /* Should be set to one if r1 is used by loadstores. */ + int stackprot = 0; + + /* All load/stores use ra. */ + if (dc->ra == 1) { + stackprot = 1; + } /* Treat the common cases first. */ if (!dc->type_b) { @@ -874,8 +893,16 @@ static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t) return &cpu_R[dc->ra]; } + if (dc->rb == 1) { + stackprot = 1; + } + *t = tcg_temp_new(); tcg_gen_add_tl(*t, cpu_R[dc->ra], cpu_R[dc->rb]); + + if (stackprot) { + gen_helper_stackprot(*t); + } return t; } /* Immediate. */ @@ -891,6 +918,9 @@ static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t) tcg_gen_add_tl(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc))); } + if (stackprot) { + gen_helper_stackprot(*t); + } return t; } @@ -1917,6 +1947,9 @@ void cpu_reset (CPUState *env) memset(env, 0, offsetof(CPUMBState, breakpoints)); tlb_flush(env, 1); + /* Disable stack protector. */ + env->shr = ~0; + env->pvr.regs[0] = PVR0_PVR_FULL_MASK \ | PVR0_USE_BARREL_MASK \ | PVR0_USE_DIV_MASK \