Patchwork microblaze: Break the tb at memory barriers

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Submitter Edgar Iglesias
Date Jan. 10, 2012, 10:27 a.m.
Message ID <1326191247-14880-3-git-send-email-edgar.iglesias@gmail.com>
Download mbox | patch
Permalink /patch/135251/
State New
Headers show

Comments

Edgar Iglesias - Jan. 10, 2012, 10:27 a.m.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
---
 target-microblaze/translate.c |   12 +++++++++++-
 1 files changed, 11 insertions(+), 1 deletions(-)

Patch

diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 180ac84..96ce2ec 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1249,12 +1249,22 @@  static void dec_bcc(DisasContext *dc)
 
 static void dec_br(DisasContext *dc)
 {
-    unsigned int dslot, link, abs;
+    unsigned int dslot, link, abs, mbar;
     int mem_index = cpu_mmu_index(dc->env);
 
     dslot = dc->ir & (1 << 20);
     abs = dc->ir & (1 << 19);
     link = dc->ir & (1 << 18);
+
+    /* Memory barrier.  */
+    mbar = (dc->ir >> 16) & 31;
+    if (mbar == 2 && dc->imm == 4) {
+        LOG_DIS("mbar %d\n", dc->rd);
+        /* Break the TB.  */
+        dc->cpustate_changed = 1;
+        return;
+    }
+
     LOG_DIS("br%s%s%s%s imm=%x\n",
              abs ? "a" : "", link ? "l" : "",
              dc->type_b ? "i" : "", dslot ? "d" : "",