Patchwork [U-Boot,1/8] powerpc/srio: Correct the register defined errors in the struct ccsr_rio_t

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Submitter Liu Gang
Date Jan. 10, 2012, 11:42 a.m.
Message ID <1326195751-20729-1-git-send-email-Gang.Liu@freescale.com>
Download mbox | patch
Permalink /patch/135224/
State Changes Requested
Headers show

Comments

Liu Gang - Jan. 10, 2012, 11:42 a.m.
Many registers were not defined in the struct ccsr_rio_t in the file
arch/powerpc/include/asm/immap_85xx.h. For example it lacks registers
from offset 0xc0600 to 0xd0160. Accordingly, some register's offset
need to be modified in the struct.

In addition, add the register's offset in the comments.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
---
 arch/powerpc/include/asm/immap_85xx.h |  338 ++++++++++++++++++++-------------
 1 files changed, 202 insertions(+), 136 deletions(-)
Wolfgang Denk - Jan. 11, 2012, 7:37 a.m.
Dear Liu Gang,

In message <1326195751-20729-1-git-send-email-Gang.Liu@freescale.com> you wrote:
> Many registers were not defined in the struct ccsr_rio_t in the file
> arch/powerpc/include/asm/immap_85xx.h. For example it lacks registers
> from offset 0xc0600 to 0xd0160. Accordingly, some register's offset
> need to be modified in the struct.

Your Subject line is way too long, make it shorter.

Also, it is not correct - the registers may be missing for some
extensions you will add, but that has not been an error so foar, so
this patch is an extension, but not a correction.

>  /* RapidIO Registers */
>  typedef struct ccsr_rio {
> -	u32	didcar;		/* Device Identity Capability */
> -	u32	dicar;		/* Device Information Capability */
> -	u32	aidcar;		/* Assembly Identity Capability */
> -	u32	aicar;		/* Assembly Information Capability */
> -	u32	pefcar;		/* Processing Element Features Capability */
> -	u32	spicar;		/* Switch Port Information Capability */
> -	u32	socar;		/* Source Operations Capability */
> -	u32	docar;		/* Destination Operations Capability */
> +	u32	didcar; /* 0xc0000 - Device Identity CAR */
> +	u32	dicar; /* 0xc0004 - Device Information CAR */
> +	u32	aidcar; /* 0xc0008 - Assembly Identity CAR */
> +	u32	aicar; /* 0xc000c - Assembly Information CAR */
> +	u32	pefcar; /* 0xc0010 - Processing Element Features CAR */
> +	u32	spicar; /* 0xc0014 - Switch Port Information CAR */
> +	u32	socar; /* 0xc0018 - Source Operations CAR */
> +	u32	docar; /* 0xc001c - Destination Operations CAR */

NAK.  We don't include offsets into the header files.  Please keep
this consistent with the rest of this file, and with other, similar
files. 

Restrict your patch on adding any new fields, and foillow the exiting
style.

Best regards,

Wolfgang Denk
Kumar Gala - Jan. 12, 2012, 4:47 p.m.
On Jan 10, 2012, at 5:42 AM, Liu Gang wrote:

> +	u32	didcar; /* 0xc0000 - Device Identity CAR */

Drop the '0xc' prefix in the comment, same comment for all registers.

- k
Liu Gang - Jan. 13, 2012, 7:12 a.m.
Hi, Kumar,

On Thu, 2012-01-12 at 10:47 -0600, Kumar Gala wrote:
> On Jan 10, 2012, at 5:42 AM, Liu Gang wrote:
> 
> > +	u32	didcar; /* 0xc0000 - Device Identity CAR */
> 
> Drop the '0xc' prefix in the comment, same comment for all registers.

Thanks, I'll rewrite this struct.

Best Regards,

Liu Gang

Patch

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 92da130..623be17 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1355,168 +1355,234 @@  typedef struct ccsr_cpm {
 
 /* RapidIO Registers */
 typedef struct ccsr_rio {
-	u32	didcar;		/* Device Identity Capability */
-	u32	dicar;		/* Device Information Capability */
-	u32	aidcar;		/* Assembly Identity Capability */
-	u32	aicar;		/* Assembly Information Capability */
-	u32	pefcar;		/* Processing Element Features Capability */
-	u32	spicar;		/* Switch Port Information Capability */
-	u32	socar;		/* Source Operations Capability */
-	u32	docar;		/* Destination Operations Capability */
+	u32	didcar; /* 0xc0000 - Device Identity CAR */
+	u32	dicar; /* 0xc0004 - Device Information CAR */
+	u32	aidcar; /* 0xc0008 - Assembly Identity CAR */
+	u32	aicar; /* 0xc000c - Assembly Information CAR */
+	u32	pefcar; /* 0xc0010 - Processing Element Features CAR */
+	u32	spicar; /* 0xc0014 - Switch Port Information CAR */
+	u32	socar; /* 0xc0018 - Source Operations CAR */
+	u32	docar; /* 0xc001c - Destination Operations CAR */
 	u8	res1[32];
-	u32	msr;		/* Mailbox Cmd And Status */
-	u32	pwdcsr;		/* Port-Write & Doorbell Cmd And Status */
+	u32	mcsr;  /* 0xc0040 - Mailbox CSR */
+	u32	pwdcsr; /* 0xc0044 - Port-Write and Doorbell CSR */
 	u8	res2[4];
-	u32	pellccsr;	/* Processing Element Logic Layer CCSR */
+	u32	pellccsr; /* 0xc004c - Processing Element Logic Layer CCSR */
 	u8	res3[12];
-	u32	lcsbacsr;	/* Local Cfg Space Base Addr Cmd & Status */
-	u32	bdidcsr;	/* Base Device ID Cmd & Status */
+	u32	lcsbacsr;	/* 0xc005c - Local Configuration Space BACSR */
+	u32	bdidcsr; /* 0xc0060 - Base Device ID CSR */
 	u8	res4[4];
-	u32	hbdidlcsr;	/* Host Base Device ID Lock Cmd & Status */
-	u32	ctcsr;		/* Component Tag Cmd & Status */
+	u32	hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock CSR */
+	u32	ctcsr; /* 0xc006c - Component Tag CSR */
 	u8	res5[144];
-	u32	pmbh0csr;	/* Port Maint. Block Hdr 0 Cmd & Status */
+	u32	pmbh0csr; /* 0xc0100 - Port Maintenance Block Header 0 CSR */
 	u8	res6[28];
-	u32	pltoccsr;	/* Port Link Time-out Ctrl Cmd & Status */
-	u32	prtoccsr;	/* Port Response Time-out Ctrl Cmd & Status */
+	u32	pltoccsr;	/* 0xc0120 - Port Link Time-out CCSR */
+	u32	prtoccsr;	/* 0xc0124 - Port Response Time-out CCSR */
 	u8	res7[20];
-	u32	pgccsr;		/* Port General Cmd & Status */
-	u32	plmreqcsr;	/* Port Link Maint. Request Cmd & Status */
-	u32	plmrespcsr;	/* Port Link Maint. Response Cmd & Status */
-	u32	plascsr;	/* Port Local Ackid Status Cmd & Status */
+	u32	pgccsr; /* 0xc013c - Port General CSR */
+	u32	plmreqcsr; /* 0xc0140 - Port Link Maintenance Request CSR */
+	u32	plmrespcsr; /* 0xc0144 - Port Link Maintenance Response CSR */
+	u32	plascsr; /* 0xc0148 - Port Local Ackid Status CSR */
 	u8	res8[12];
-	u32	pescsr;		/* Port Error & Status Cmd & Status */
-	u32	pccsr;		/* Port Control Cmd & Status */
-	u8	res9[65184];
-	u32	cr;		/* Port Control Cmd & Status */
-	u8	res10[12];
-	u32	pcr;		/* Port Configuration */
-	u32	peir;		/* Port Error Injection */
-	u8	res11[3048];
-	u32	rowtar0;	/* RIO Outbound Window Translation Addr 0 */
-	u8	res12[12];
-	u32	rowar0;		/* RIO Outbound Attrs 0 */
+	u32	pescsr; /* 0xc0158 - Port Error and Status CSR */
+	u32	pccsr; /* 0xc015c - Port Control CSR */
+	u8	res9[1184];
+	u32	erbh; /* 0xc0600 - Error Reporting Block Header Register */
+	u8	res10[4];
+	u32	ltledcsr; /* 0xc0608 - Logical/Transport layer error DCSR */
+	u32	ltleecsr; /* 0xc060c - Logical/Transport layer error ECSR */
+	u8	res11[4];
+	u32	ltlaccsr; /* 0xc0614 - Logical/Transport layer ACCSR */
+	u32	ltldidccsr; /* 0xc0618 - Logical/Transport layer DID CCSR */
+	u32	ltlcccsr; /* 0xc061c - Logical/Transport layer control CCSR */
+	u8	res12[32];
+	u32	edcsr; /* 0xc0640 - Port 0 error detect CSR */
+	u32	erecsr; /* 0xc0644 - Port 0 error rate enable CSR */
+	u32	ecacsr; /* 0xc0648 - Port 0 error capture attributes CSR */
+	u32	pcseccsr0; /* 0xc064c - Port 0 packet/control symbol ECCSR 0 */
+	u32	peccsr1; /* 0xc0650 - Port 0 error capture CSR 1 */
+	u32	peccsr2; /* 0xc0654 - Port 0 error capture CSR 2 */
+	u32	peccsr3; /* 0xc0658 - Port 0 error capture CSR 3 */
 	u8	res13[12];
-	u32	rowtar1;	/* RIO Outbound Window Translation Addr 1 */
-	u8	res14[4];
-	u32	rowbar1;	/* RIO Outbound Window Base Addr 1 */
-	u8	res15[4];
-	u32	rowar1;		/* RIO Outbound Attrs 1 */
+	u32	ercsr; /* 0xc0668 - Port 0 error rate CSR */
+	u32	ertcsr; /* 0xc066C - Port 0 error rate threshold CSR */
+	u8	res14[63892];
+	u32	llcr; /* 0xd0004 - Logical Layer Configuration Register */
+	u8	res15[8];
+	u32	epwisr; /* 0xd0010 - Error / Port-Write Interrupt SR */
 	u8	res16[12];
-	u32	rowtar2;	/* RIO Outbound Window Translation Addr 2 */
-	u8	res17[4];
-	u32	rowbar2;	/* RIO Outbound Window Base Addr 2 */
-	u8	res18[4];
-	u32	rowar2;		/* RIO Outbound Attrs 2 */
-	u8	res19[12];
-	u32	rowtar3;	/* RIO Outbound Window Translation Addr 3 */
-	u8	res20[4];
-	u32	rowbar3;	/* RIO Outbound Window Base Addr 3 */
-	u8	res21[4];
-	u32	rowar3;		/* RIO Outbound Attrs 3 */
-	u8	res22[12];
-	u32	rowtar4;	/* RIO Outbound Window Translation Addr 4 */
+	u32	lretcr; /* 0xd0020 - Logical Retry Error Threshold CR */
+	u8	res17[92];
+	u32	pretcr; /* 0xd0080 - Physical Retry Erorr Threshold CR */
+	u8	res18[124];
+	u32	adidcsr; /* 0xd0100 - Port 0 Alt. Device ID CSR */
+	u8	res19[28];
+	u32	ptaacr; /* 0xd0120 - Port 0 Pass-Through/Accept-All CR */
+	u8	res20[12];
+	u32	iecsr; /* 0xd0130 - Port 0 Implementation Error CSR */
+	u8	res21[12];
+	u32	pcr; /* 0xd0140 - Port 0 Phsyical Configuration Register */
+	u8	res22[20];
+	u32	slcsr; /* 0xd0158 - Port 0 Serial Link CSR */
 	u8	res23[4];
-	u32	rowbar4;	/* RIO Outbound Window Base Addr 4 */
-	u8	res24[4];
-	u32	rowar4;		/* RIO Outbound Attrs 4 */
-	u8	res25[12];
-	u32	rowtar5;	/* RIO Outbound Window Translation Addr 5 */
-	u8	res26[4];
-	u32	rowbar5;	/* RIO Outbound Window Base Addr 5 */
+	u32	sleir; /* 0xd0160 - Port 0 Serial Link Error Injection */
+	u8	res24[2716];
+	u32	rowtar0; /* 0xd0c00 - RapidIO Outbound Window TAR 0 */
+	u32	rowtear0; /* 0xd0c04 - RapidIO Outbound Window TEAR 0 */
+	u8	res25[8];
+	u32	rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */
+	u8	res26[12];
+	u32	rowtar1; /* 0xd0c20 - RapidIO Outbound Window TAR 1 */
+	u32	rowtear1; /* 0xd0c24 - RapidIO Outbound Window TEAR 1 */
+	u32	rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base AR 1 */
 	u8	res27[4];
-	u32	rowar5;		/* RIO Outbound Attrs 5 */
-	u8	res28[12];
-	u32	rowtar6;	/* RIO Outbound Window Translation Addr 6 */
+	u32	rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */
+	u32	rows1r1; /* 0xd0c34 - RapidIO Outbound Window S 1 R1 */
+	u32	rows2r1; /* 0xd0c38 - RapidIO Outbound Window S 2 R 1 */
+	u32	rows3r1; /* 0xd0c3c - RapidIO Outbound Window S 3 R 1 */
+	u32	rowtar2; /* 0xd0c40 - RapidIO Outbound Window TAR 2 */
+	u32	rowtear2; /* 0xd0c44 - RapidIO Outbound Window TEAR 2 */
+	u32	rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base AR 2 */
+	u8	res28[4];
+	u32	rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */
+	u32	rows1r2; /* 0xd0c54 - RapidIO Outbound Window S 1 R 2 */
+	u32	rows2r2; /* 0xd0c58 - RapidIO Outbound Window S 2 R 2 */
+	u32	rows3r2; /* 0xd0c5c - RapidIO Outbound Window S 3 R 2 */
+	u32	rowtar3; /* 0xd0c60 - RapidIO Outbound Window TAR 3 */
+	u32	rowtear3; /* 0xd0c64 - RapidIO Outbound Window TEAR 3 */
+	u32	rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base AR 3 */
 	u8	res29[4];
-	u32	rowbar6;	/* RIO Outbound Window Base Addr 6 */
+	u32	rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */
+	u32	rows1r3; /* 0xd0c74 - RapidIO Outbound Window S 1 R 3 */
+	u32	rows2r3; /* 0xd0c78 - RapidIO Outbound Window S 2 R 3 */
+	u32	rows3r3; /* 0xd0c7c - RapidIO Outbound Window S 3 R 3 */
+	u32	rowtar4; /* 0xd0c80 - RapidIO Outbound Window TAR 4 */
+	u32	rowtear4; /* 0xd0c84 - RapidIO Outbound Window TEAR 4 */
+	u32	rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base AR 4 */
 	u8	res30[4];
-	u32	rowar6;		/* RIO Outbound Attrs 6 */
-	u8	res31[12];
-	u32	rowtar7;	/* RIO Outbound Window Translation Addr 7 */
+	u32	rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */
+	u32	rows1r4; /* 0xd0c94 - RapidIO Outbound Window S 1 R 4 */
+	u32	rows2r4; /* 0xd0c98 - RapidIO Outbound Window S 2 R 4 */
+	u32	rows3r4; /* 0xd0c9c - RapidIO Outbound Window S 3 R 4 */
+	u32	rowtar5; /* 0xd0ca0 - RapidIO Outbound Window TAR 5 */
+	u32	rowtear5; /* 0xd0ca4 - RapidIO Outbound Window TEAR 5 */
+	u32	rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base AR 5 */
+	u8	res31[4];
+	u32	rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */
+	u32	rows1r5; /* 0xd0cb4 - RapidIO Outbound Window S 1 R 5 */
+	u32	rows2r5; /* 0xd0cb8 - RapidIO Outbound Window S 2 R 5 */
+	u32	rows3r5; /* 0xd0cbc - RapidIO Outbound Window S 3 R 5 */
+	u32	rowtar6; /* 0xd0cc0 - RapidIO Outbound Window TAR 6 */
+	u32	rowtear6; /* 0xd0cc4 - RapidIO Outbound Window TEAR 6 */
+	u32	rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base AR 6 */
 	u8	res32[4];
-	u32	rowbar7;	/* RIO Outbound Window Base Addr 7 */
+	u32	rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */
+	u32	rows1r6; /* 0xd0cd4 - RapidIO Outbound Window S 1 R 6 */
+	u32	rows2r6; /* 0xd0cd8 - RapidIO Outbound Window S 2 R 6 */
+	u32	rows3r6; /* 0xd0cdc - RapidIO Outbound Window S 3 R 6 */
+	u32	rowtar7; /* 0xd0ce0 - RapidIO Outbound Window TAR 7 */
+	u32	rowtear7; /* 0xd0ce4 - RapidIO Outbound Window TEAR 7 */
+	u32	rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base AR 7 */
 	u8	res33[4];
-	u32	rowar7;		/* RIO Outbound Attrs 7 */
-	u8	res34[12];
-	u32	rowtar8;	/* RIO Outbound Window Translation Addr 8 */
-	u8	res35[4];
-	u32	rowbar8;	/* RIO Outbound Window Base Addr 8 */
+	u32	rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */
+	u32	rows1r7; /* 0xd0cf4 - RapidIO Outbound Window S 1 R 7 */
+	u32	rows2r7; /* 0xd0cf8 - RapidIO Outbound Window S 2 R 7 */
+	u32	rows3r7; /* 0xd0cfc - RapidIO Outbound Window S 3 R 7 */
+	u32	rowtar8; /* 0xd0d00 - RapidIO Outbound Window TAR 8 */
+	u32	rowtear8; /* 0xd0d04 - RapidIO Outbound Window TEAR 8 */
+	u32	rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base AR 8 */
+	u8	res34[4];
+	u32	rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */
+	u32	rows1r8; /* 0xd0d14 - RapidIO Outbound Window S 1 R 8 */
+	u32	rows2r8; /* 0xd0d18 - RapidIO Outbound Window S 2 R 8 */
+	u32	rows3r8; /* 0xd0d1c - RapidIO Outbound Window S 3 R 8 */
+	u8	res35[64];
+	u32	riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation AR 4 */
+	u8 res59[4];
+	u32	riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base AR 4 */
 	u8	res36[4];
-	u32	rowar8;		/* RIO Outbound Attrs 8 */
-	u8	res37[76];
-	u32	riwtar4;	/* RIO Inbound Window Translation Addr 4 */
+	u32	riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */
+	u8	res37[12];
+	u32	riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation AR 3 */
 	u8	res38[4];
-	u32	riwbar4;	/* RIO Inbound Window Base Addr 4 */
+	u32	riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base AR 3 */
 	u8	res39[4];
-	u32	riwar4;		/* RIO Inbound Attrs 4 */
+	u32	riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */
 	u8	res40[12];
-	u32	riwtar3;	/* RIO Inbound Window Translation Addr 3 */
+	u32	riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation AR 2 */
 	u8	res41[4];
-	u32	riwbar3;	/* RIO Inbound Window Base Addr 3 */
+	u32	riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base AR 2 */
 	u8	res42[4];
-	u32	riwar3;		/* RIO Inbound Attrs 3 */
+	u32	riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */
 	u8	res43[12];
-	u32	riwtar2;	/* RIO Inbound Window Translation Addr 2 */
+	u32	riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation AR 1 */
 	u8	res44[4];
-	u32	riwbar2;	/* RIO Inbound Window Base Addr 2 */
+	u32	riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base AR 1 */
 	u8	res45[4];
-	u32	riwar2;		/* RIO Inbound Attrs 2 */
+	u32	riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */
 	u8	res46[12];
-	u32	riwtar1;	/* RIO Inbound Window Translation Addr 1 */
-	u8	res47[4];
-	u32	riwbar1;	/* RIO Inbound Window Base Addr 1 */
-	u8	res48[4];
-	u32	riwar1;		/* RIO Inbound Attrs 1 */
-	u8	res49[12];
-	u32	riwtar0;	/* RIO Inbound Window Translation Addr 0 */
-	u8	res50[12];
-	u32	riwar0;		/* RIO Inbound Attrs 0 */
-	u8	res51[12];
-	u32	pnfedr;		/* Port Notification/Fatal Error Detect */
-	u32	pnfedir;	/* Port Notification/Fatal Error Detect */
-	u32	pnfeier;	/* Port Notification/Fatal Error IRQ Enable */
-	u32	pecr;		/* Port Error Control */
-	u32	pepcsr0;	/* Port Error Packet/Control Symbol 0 */
-	u32	pepr1;		/* Port Error Packet 1 */
-	u32	pepr2;		/* Port Error Packet 2 */
-	u8	res52[4];
-	u32	predr;		/* Port Recoverable Error Detect */
-	u8	res53[4];
-	u32	pertr;		/* Port Error Recovery Threshold */
-	u32	prtr;		/* Port Retry Threshold */
-	u8	res54[464];
-	u32	omr;		/* Outbound Mode */
-	u32	osr;		/* Outbound Status */
-	u32	eodqtpar;	/* Extended Outbound Desc Queue Tail Ptr Addr */
-	u32	odqtpar;	/* Outbound Desc Queue Tail Ptr Addr */
-	u32	eosar;		/* Extended Outbound Unit Source Addr */
-	u32	osar;		/* Outbound Unit Source Addr */
-	u32	odpr;		/* Outbound Destination Port */
-	u32	odatr;		/* Outbound Destination Attrs */
-	u32	odcr;		/* Outbound Doubleword Count */
-	u32	eodqhpar;	/* Extended Outbound Desc Queue Head Ptr Addr */
-	u32	odqhpar;	/* Outbound Desc Queue Head Ptr Addr */
-	u8	res55[52];
-	u32	imr;		/* Outbound Mode */
-	u32	isr;		/* Inbound Status */
-	u32	eidqtpar;	/* Extended Inbound Desc Queue Tail Ptr Addr */
-	u32	idqtpar;	/* Inbound Desc Queue Tail Ptr Addr */
-	u32	eifqhpar;	/* Extended Inbound Frame Queue Head Ptr Addr */
-	u32	ifqhpar;	/* Inbound Frame Queue Head Ptr Addr */
-	u8	res56[1000];
-	u32	dmr;		/* Doorbell Mode */
-	u32	dsr;		/* Doorbell Status */
-	u32	edqtpar;	/* Extended Doorbell Queue Tail Ptr Addr */
-	u32	dqtpar;		/* Doorbell Queue Tail Ptr Addr */
-	u32	edqhpar;	/* Extended Doorbell Queue Head Ptr Addr */
-	u32	dqhpar;		/* Doorbell Queue Head Ptr Addr */
-	u8	res57[104];
-	u32	pwmr;		/* Port-Write Mode */
-	u32	pwsr;		/* Port-Write Status */
-	u32	epwqbar;	/* Extended Port-Write Queue Base Addr */
-	u32	pwqbar;		/* Port-Write Queue Base Addr */
-	u8	res58[60176];
+	u32	riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation AR 0 */
+	u8	res47[12];
+	u32	riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */
+	u8	res48[12];
+	u32	pnfedr; /* 0xd0e00 - Port Notification/Fatal Error DR */
+	u32	pnfedir; /* 0xd0e04 - Port Notification/Fatal Error DR */
+	u32	pnfeier; /* 0xd0e08 - Port Notification/Fatal Error IER */
+	u32	pecr; /* 0xd0e0c - Port Error Control Register */
+	u32	pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol 0 */
+	u32	pepr1; /* 0xd0e14 - Port Error Packet Register 1 */
+	u32	pepr2; /* 0xd0e18 - Port Error Packet Register 2 */
+	u8	res49[4];
+	u32	predr; /* 0xd0e20 - Port Recoverable Error Detect Register */
+	u8	res50[4];
+	u32	pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */
+	u32	prtr;	 /* 0xd0e2c - Port Retry Threshold Register */
+	u8	res51[8656];
+	u32	omr; /* 0xd3000 - Outbound Mode Register */
+	u32	osr; /* 0xd3004 - Outbound Status Register */
+	u32	eodqdpar; /* 0xd3008 - Extended Outbound DQ DPAR */
+	u32	odqdpar; /* 0xd300c - Outbound Descriptor Queue DPAR */
+	u32	eosar; /* 0xd3010 - Extended Outbound Unit Source AR */
+	u32	osar; /* 0xd3014 - Outbound Unit Source AR */
+	u32	odpr; /* 0xd3018 - Outbound Destination Port Register */
+	u32	odatr; /* 0xd301c - Outbound Destination Attributes Register */
+	u32	odcr; /* 0xd3020 - Outbound Doubleword Count Register */
+	u32	eodqepar; /* 0xd3024 - Extended Outbound DQ EPAR */
+	u32	odqepar; /* 0xd3028 - Outbound Descriptor Queue EPAR */
+	u32	oretr; /* 0xd302C - Outbound Retry Error Threshold Register */
+	u32	omgr; /* 0xd3030 - Outbound Multicast Group Register */
+	u32	omlr; /* 0xd3034 - Outbound Multicast List Register */
+	u8	res52[40];
+	u32	imr;	 /* 0xd3060 - Outbound Mode Register */
+	u32	isr; /* 0xd3064 - Inbound Status Register */
+	u32	eidqdpar; /* 0xd3068 - Extended Inbound Descriptor Queue DPAR */
+	u32	idqdpar; /* 0xd306c - Inbound Descriptor Queue DPAR */
+	u32	eifqepar; /* 0xd3070 - Extended Inbound Frame Queue EPAR */
+	u32	ifqepar; /* 0xd3074 - Inbound Frame Queue EPAR */
+	u32	imirir; /* 0xd3078 - Inbound Maximum Interrutp RIR */
+	u8	res53[900];
+	u32	oddmr; /* 0xd3400 - Outbound Doorbell Mode Register */
+	u32	oddsr; /* 0xd3404 - Outbound Doorbell Status Register */
+	u8	res54[16];
+	u32	oddpr; /* 0xd3418 - Outbound Doorbell Destination Port */
+	u32	oddatr; /* 0xd341C - Outbound Doorbell Destination AR */
+	u8	res55[12];
+	u32	oddretr; /* 0xd342C - Outbound Doorbell Retry Threshold CR */
+	u8	res56[48];
+	u32	idmr; /* 0xd3460 - Inbound Doorbell Mode Register */
+	u32	idsr;	 /* 0xd3464 - Inbound Doorbell Status Register */
+	u32	iedqdpar; /* 0xd3468 - Extended Inbound Doorbell Queue DPAR */
+	u32	iqdpar; /* 0xd346c - Inbound Doorbell Queue DPAR */
+	u32	iedqepar; /* 0xd3470 - Extended Inbound Doorbell Queue EPAR */
+	u32	idqepar; /* 0xd3474 - Inbound Doorbell Queue EPAR */
+	u32	idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt RIR */
+	u8	res57[100];
+	u32	pwmr; /* 0xd34e0 - Port-Write Mode Register */
+	u32	pwsr; /* 0xd34e4 - Port-Write Status Register */
+	u32	epwqbar; /* 0xd34e8 - Extended Port-Write Queue BAR */
+	u32	pwqbar; /* 0xd34ec - Port-Write Queue Base Address Register */
+	u8	res58[51984];
 } ccsr_rio_t;
 
 /* Quick Engine Block Pin Muxing Registers */