Patchwork [U-Boot] mx28: fix clearing of IRQs in power init

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Submitter Zach Sadecki
Date Jan. 9, 2012, 8:22 p.m.
Message ID <4F0B4C9E.5060306@itwatchdogs.com>
Download mbox | patch
Permalink /patch/135119/
State Awaiting Upstream
Delegated to: Stefano Babic
Headers show

Comments

Zach Sadecki - Jan. 9, 2012, 8:22 p.m.
There are 2 locations in the power init code for the mx28 where IRQs are not being cleared because incorrect methods to clear those bits were being used.  This was causing my board to get stuck waiting for POWER_CTRL_VDD5V_DROOP_IRQ to clear.  Using the correct method to clear the IRQs fixes it.

Signed-off-by: Zach Sadecki <zach@itwatchdogs.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
 arch/arm/cpu/arm926ejs/mx28/spl_power_init.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)
Marek Vasut - Jan. 9, 2012, 11:10 p.m.
> There are 2 locations in the power init code for the mx28 where IRQs are
> not being cleared because incorrect methods to clear those bits were being
> used.  This was causing my board to get stuck waiting for
> POWER_CTRL_VDD5V_DROOP_IRQ to clear.  Using the correct method to clear
> the IRQs fixes it.
> 
> Signed-off-by: Zach Sadecki <zach@itwatchdogs.com>
> Cc: Wolfgang Denk <wd@denx.de>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
>  arch/arm/cpu/arm926ejs/mx28/spl_power_init.c |    8 ++++----
>  1 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
> b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c index a4dc2a3..380b120
> 100644
> --- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
> +++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
> @@ -240,8 +240,8 @@ void mx28_enable_4p2_dcdc_input(int xfer)
>  		clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
> 
>  	while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
> -		clrbits_le32(&power_regs->hw_power_ctrl,
> -				POWER_CTRL_VBUS_VALID_IRQ);
> +		writel(POWER_CTRL_VBUS_VALID_IRQ,
> +			&power_regs->hw_power_ctrl_clr);
> 
>  	if (prev_5v_brnout) {
>  		writel(POWER_5VCTRL_PWDN_5VBRNOUT,
> @@ -256,8 +256,8 @@ void mx28_enable_4p2_dcdc_input(int xfer)
>  	}
> 
>  	while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
> -		clrbits_le32(&power_regs->hw_power_ctrl,
> -				POWER_CTRL_VDD5V_DROOP_IRQ);
> +		writel(POWER_CTRL_VDD5V_DROOP_IRQ,
> +			&power_regs->hw_power_ctrl_clr);
> 
>  	if (prev_5v_droop)
>  		clrbits_le32(&power_regs->hw_power_ctrl,

Hello,

this is an impressive catch! I did investigation of the Freescale bootlets code 
and found out you're right, it's an SCT register. So:

Acked-by: Marek Vasut <marek.vasut@gmail.com>

M
Stefano Babic - Jan. 11, 2012, 8:06 a.m.
On 09/01/2012 21:22, Zach Sadecki wrote:
> There are 2 locations in the power init code for the mx28 where IRQs are not being cleared because incorrect methods to clear those bits were being used.  This was causing my board to get stuck waiting for POWER_CTRL_VDD5V_DROOP_IRQ to clear.  Using the correct method to clear the IRQs fixes it.
> 
> Signed-off-by: Zach Sadecki <zach@itwatchdogs.com>
> Cc: Wolfgang Denk <wd@denx.de>
> Cc: Stefano Babic <sbabic@denx.de>
> ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

Patch

diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
index a4dc2a3..380b120 100644
--- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
@@ -240,8 +240,8 @@  void mx28_enable_4p2_dcdc_input(int xfer)
 		clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
 
 	while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
-		clrbits_le32(&power_regs->hw_power_ctrl,
-				POWER_CTRL_VBUS_VALID_IRQ);
+		writel(POWER_CTRL_VBUS_VALID_IRQ,
+			&power_regs->hw_power_ctrl_clr);
 
 	if (prev_5v_brnout) {
 		writel(POWER_5VCTRL_PWDN_5VBRNOUT,
@@ -256,8 +256,8 @@  void mx28_enable_4p2_dcdc_input(int xfer)
 	}
 
 	while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
-		clrbits_le32(&power_regs->hw_power_ctrl,
-				POWER_CTRL_VDD5V_DROOP_IRQ);
+		writel(POWER_CTRL_VDD5V_DROOP_IRQ,
+			&power_regs->hw_power_ctrl_clr);
 
 	if (prev_5v_droop)
 		clrbits_le32(&power_regs->hw_power_ctrl,