From patchwork Sat Jan 7 20:09:38 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 134863 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 243DDB6F69 for ; Sun, 8 Jan 2012 07:10:24 +1100 (EST) Received: from localhost ([::1]:34461 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rjcag-0004Tx-R5 for incoming@patchwork.ozlabs.org; Sat, 07 Jan 2012 15:10:10 -0500 Received: from eggs.gnu.org ([140.186.70.92]:39604) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RjcaP-0004HN-16 for qemu-devel@nongnu.org; Sat, 07 Jan 2012 15:09:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RjcaM-0001et-LR for qemu-devel@nongnu.org; Sat, 07 Jan 2012 15:09:52 -0500 Received: from hall.aurel32.net ([88.191.126.93]:43921) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RjcaM-0001ei-Gn; Sat, 07 Jan 2012 15:09:50 -0500 Received: from [2001:470:d4ed:0:5e26:aff:fe2b:6f5b] (helo=volta.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.72) (envelope-from ) id 1RjcaL-0004CK-Nh; Sat, 07 Jan 2012 21:09:49 +0100 Received: from aurel32 by volta.aurel32.net with local (Exim 4.77) (envelope-from ) id 1RjcaK-0000Ky-Jb; Sat, 07 Jan 2012 21:09:48 +0100 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Sat, 7 Jan 2012 21:09:38 +0100 Message-Id: <1325966978-940-5-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1325966978-940-1-git-send-email-aurelien@aurel32.net> References: <1325966978-940-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 88.191.126.93 Cc: qemu-stable@nongnu.org, Aurelien Jarno Subject: [Qemu-devel] [PATCH 4/4] target-i386: fix SSE rounding and flush to zero X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org SSE rounding and flush to zero control has never been implemented. However given that softfloat-native was using a single state for FPU and SSE and given that glibc is setting both FPU and SSE state in fesetround(), this was working correctly up to the switch to softfloat. Fix that by adding an update_sse_status() function similar to update_fpu_status(), and callin git on write to mxcsr. Signed-off-by: Aurelien Jarno --- target-i386/helper.h | 1 + target-i386/op_helper.c | 64 +++++++++++++++++++++++++++++++++++++++------- target-i386/translate.c | 2 +- 3 files changed, 56 insertions(+), 11 deletions(-) diff --git a/target-i386/helper.h b/target-i386/helper.h index 6b518ad..761954e 100644 --- a/target-i386/helper.h +++ b/target-i386/helper.h @@ -197,6 +197,7 @@ DEF_HELPER_2(lzcnt, tl, tl, int) /* MMX/SSE */ +DEF_HELPER_1(ldmxcsr, void, i32) DEF_HELPER_0(enter_mmx, void) DEF_HELPER_0(emms, void) DEF_HELPER_2(movq, void, ptr, ptr) diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c index c89e4a4..2aea71b 100644 --- a/target-i386/op_helper.c +++ b/target-i386/op_helper.c @@ -52,11 +52,11 @@ static inline target_long lshift(target_long x, int n) } } -#define RC_MASK 0xc00 -#define RC_NEAR 0x000 -#define RC_DOWN 0x400 -#define RC_UP 0x800 -#define RC_CHOP 0xc00 +#define FPU_RC_MASK 0xc00 +#define FPU_RC_NEAR 0x000 +#define FPU_RC_DOWN 0x400 +#define FPU_RC_UP 0x800 +#define FPU_RC_CHOP 0xc00 #define MAXTAN 9223372036854775808.0 @@ -4024,18 +4024,18 @@ static void update_fp_status(void) int rnd_type; /* set rounding mode */ - switch(env->fpuc & RC_MASK) { + switch(env->fpuc & FPU_RC_MASK) { default: - case RC_NEAR: + case FPU_RC_NEAR: rnd_type = float_round_nearest_even; break; - case RC_DOWN: + case FPU_RC_DOWN: rnd_type = float_round_down; break; - case RC_UP: + case FPU_RC_UP: rnd_type = float_round_up; break; - case RC_CHOP: + case FPU_RC_CHOP: rnd_type = float_round_to_zero; break; } @@ -5629,6 +5629,50 @@ void helper_vmexit(uint32_t exit_code, uint64_t exit_info_1) /* MMX/SSE */ /* XXX: optimize by storing fptt and fptags in the static cpu state */ + +#define SSE_DAZ 0x0040 +#define SSE_RC_MASK 0x6000 +#define SSE_RC_NEAR 0x0000 +#define SSE_RC_DOWN 0x2000 +#define SSE_RC_UP 0x4000 +#define SSE_RC_CHOP 0x6000 +#define SSE_FZ 0x8000 + +static void update_sse_status(void) +{ + int rnd_type; + + /* set rounding mode */ + switch(env->mxcsr & SSE_RC_MASK) { + default: + case SSE_RC_NEAR: + rnd_type = float_round_nearest_even; + break; + case SSE_RC_DOWN: + rnd_type = float_round_down; + break; + case SSE_RC_UP: + rnd_type = float_round_up; + break; + case SSE_RC_CHOP: + rnd_type = float_round_to_zero; + break; + } + set_float_rounding_mode(rnd_type, &env->sse_status); + + /* set denormals are zero */ + set_flush_inputs_to_zero((env->mxcsr & SSE_DAZ) ? 1 : 0, &env->sse_status); + + /* set flush to zero */ + set_flush_to_zero((env->mxcsr & SSE_FZ) ? 1 : 0, &env->fp_status); +} + +void helper_ldmxcsr(uint32_t val) +{ + env->mxcsr = val; + update_sse_status(); +} + void helper_enter_mmx(void) { env->fpstt = 0; diff --git a/target-i386/translate.c b/target-i386/translate.c index 8321bf3..b9839c5 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -7544,7 +7544,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_lea_modrm(s, modrm, ®_addr, &offset_addr); if (op == 2) { gen_op_ld_T0_A0(OT_LONG + s->mem_index); - tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr)); + gen_helper_ldmxcsr(cpu_T[0]); } else { tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr)); gen_op_st_T0_A0(OT_LONG + s->mem_index);