Patchwork [U-Boot,v2,3/4] OMAP4: clock-common: Move the usb dppl configuration to new func

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Submitter Govindraj.R
Date Jan. 6, 2012, 9:04 a.m.
Message ID <1325840641-26580-4-git-send-email-govindraj.raja@ti.com>
Download mbox | patch
Permalink /patch/134618/
State Accepted
Delegated to: Marek Vasut
Headers show

Comments

Govindraj.R - Jan. 6, 2012, 9:04 a.m.
From: "Govindraj.R" <govindraj.raja@ti.com>

usb dpll configuration is done only part of non-essential
dppl configuration however if CONFIG_USB_EHCI_OMAP is defined
we may have to configure usb dpll's for proper functioning
of usb modules. So move the usb dppl configuration to a new func.
and utilise the same during essential dpll configuration.

Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
---
 arch/arm/cpu/armv7/omap-common/clocks-common.c |   52 ++++++++++++++---------
 1 files changed, 32 insertions(+), 20 deletions(-)

Patch

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 1da90a4..770ac19 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -251,6 +251,33 @@  void configure_mpu_dpll(void)
 	debug("MPU DPLL locked\n");
 }
 
+static void setup_usb_dpll(void)
+{
+	const struct dpll_params *params;
+	u32 sys_clk_khz, sd_div, num, den;
+
+	sys_clk_khz = get_sys_clk_freq() / 1000;
+	/*
+	 * USB:
+	 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
+	 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
+	 *      - where CLKINP is sys_clk in MHz
+	 * Use CLKINP in KHz and adjust the denominator accordingly so
+	 * that we have enough accuracy and at the same time no overflow
+	 */
+	params = get_usb_dpll_params();
+	num = params->m * sys_clk_khz;
+	den = (params->n + 1) * 250 * 1000;
+	num += den - 1;
+	sd_div = num / den;
+	clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
+			CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
+			sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
+
+	/* Now setup the dpll with the regular function */
+	do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
+}
+
 static void setup_dplls(void)
 {
 	u32 temp;
@@ -282,13 +309,16 @@  static void setup_dplls(void)
 
 	/* MPU dpll */
 	configure_mpu_dpll();
+
+#ifdef CONFIG_USB_EHCI_OMAP
+	setup_usb_dpll();
+#endif
 }
 
 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
 static void setup_non_essential_dplls(void)
 {
 	u32 sys_clk_khz, abe_ref_clk;
-	u32 sd_div, num, den;
 	const struct dpll_params *params;
 
 	sys_clk_khz = get_sys_clk_freq() / 1000;
@@ -300,25 +330,7 @@  static void setup_non_essential_dplls(void)
 	params = get_iva_dpll_params();
 	do_setup_dpll(&prcm->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
 
-	/*
-	 * USB:
-	 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
-	 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
-	 *      - where CLKINP is sys_clk in MHz
-	 * Use CLKINP in KHz and adjust the denominator accordingly so
-	 * that we have enough accuracy and at the same time no overflow
-	 */
-	params = get_usb_dpll_params();
-	num = params->m * sys_clk_khz;
-	den = (params->n + 1) * 250 * 1000;
-	num += den - 1;
-	sd_div = num / den;
-	clrsetbits_le32(&prcm->cm_clksel_dpll_usb,
-			CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
-			sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
-
-	/* Now setup the dpll with the regular function */
-	do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
+	setup_usb_dpll();
 
 	/* Configure ABE dpll */
 	params = get_abe_dpll_params();