Patchwork [U-Boot,v2,09/17] x86: Create weak init_cache() and default enable_caches() functions

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Submitter Graeme Russ
Date Jan. 4, 2012, 7:59 p.m.
Message ID <1325707195-3218-9-git-send-email-graeme.russ@gmail.com>
Download mbox | patch
Permalink /patch/134346/
State Awaiting Upstream
Delegated to: Graeme Russ
Headers show

Comments

Graeme Russ - Jan. 4, 2012, 7:59 p.m.
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
---
Changes for v2:
 - Tweaked commit title

 arch/x86/cpu/cpu.c                |   18 +++++++++++++++---
 arch/x86/include/asm/u-boot-x86.h |    1 +
 arch/x86/lib/board.c              |    1 +
 3 files changed, 17 insertions(+), 3 deletions(-)

--
1.7.5.2.317.g391b14
Simon Glass - Jan. 12, 2012, 4:55 a.m.
Hi Graeme,

On Wed, Jan 4, 2012 at 11:59 AM, Graeme Russ <graeme.russ@gmail.com> wrote:
> Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
> ---
> Changes for v2:
>  - Tweaked commit title
>
>  arch/x86/cpu/cpu.c                |   18 +++++++++++++++---
>  arch/x86/include/asm/u-boot-x86.h |    1 +
>  arch/x86/lib/board.c              |    1 +
>  3 files changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
> index 8c3b92c..e9bb0d7 100644
> --- a/arch/x86/cpu/cpu.c
> +++ b/arch/x86/cpu/cpu.c
> @@ -140,6 +140,14 @@ int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f")));
>
>  int x86_cpu_init_r(void)
>  {
> +       /* Initialize core interrupt and exception functionality of CPU */
> +       cpu_init_interrupts();
> +       return 0;
> +}
> +int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
> +
> +void x86_enable_caches(void)
> +{
>        const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD);
>
>        /* turn on the cache and disable write through */
> @@ -147,12 +155,16 @@ int x86_cpu_init_r(void)
>            "andl       %0, %%eax\n"
>            "movl       %%eax, %%cr0\n"
>            "wbinvd\n" : : "i" (nw_cd_rst) : "eax");
> +}
> +void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
> +
> +int x86_init_cache(void)
> +{
> +       enable_caches();

One question on this patch - it looks like init_cache() just called
enable_caches(). Both are weak functions. Is there any reason for
having two?

Is it possible to have init_cache() just be the weak function which
defaults to what you have here for x86_enable_caches()?

Regards,
Simon

>
> -       /* Initialize core interrupt and exception functionality of CPU */
> -       cpu_init_interrupts();
>        return 0;
>  }
> -int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
> +int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
>
>  int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
>  {
> diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
> index 5540d51..878a1ee 100644
> --- a/arch/x86/include/asm/u-boot-x86.h
> +++ b/arch/x86/include/asm/u-boot-x86.h
> @@ -39,6 +39,7 @@ int x86_cpu_init_f(void);
>  int cpu_init_f(void);
>  void init_gd(gd_t *id, u64 *gdt_addr);
>  void setup_gdt(gd_t *id, u64 *gdt_addr);
> +int init_cache(void);
>
>  /* cpu/.../timer.c */
>  void timer_isr(void *);
> diff --git a/arch/x86/lib/board.c b/arch/x86/lib/board.c
> index 3d82165..56acf35 100644
> --- a/arch/x86/lib/board.c
> +++ b/arch/x86/lib/board.c
> @@ -140,6 +140,7 @@ init_fnc_t *init_sequence_f[] = {
>
>  init_fnc_t *init_sequence_r[] = {
>        copy_gd_to_ram,
> +       init_cache,
>        cpu_init_r,             /* basic cpu dependent setup */
>        board_early_init_r,     /* basic board dependent setup */
>        dram_init,              /* configure available RAM banks */
> --
> 1.7.5.2.317.g391b14
>
> _______________________________________________
> U-Boot mailing list
> U-Boot@lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot

Patch

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index 8c3b92c..e9bb0d7 100644
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -140,6 +140,14 @@  int cpu_init_f(void) __attribute__((weak, alias("x86_cpu_init_f")));

 int x86_cpu_init_r(void)
 {
+	/* Initialize core interrupt and exception functionality of CPU */
+	cpu_init_interrupts();
+	return 0;
+}
+int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
+
+void x86_enable_caches(void)
+{
 	const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD);

 	/* turn on the cache and disable write through */
@@ -147,12 +155,16 @@  int x86_cpu_init_r(void)
 	    "andl	%0, %%eax\n"
 	    "movl	%%eax, %%cr0\n"
 	    "wbinvd\n" : : "i" (nw_cd_rst) : "eax");
+}
+void enable_caches(void) __attribute__((weak, alias("x86_enable_caches")));
+
+int x86_init_cache(void)
+{
+	enable_caches();

-	/* Initialize core interrupt and exception functionality of CPU */
-	cpu_init_interrupts();
 	return 0;
 }
-int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r")));
+int init_cache(void) __attribute__((weak, alias("x86_init_cache")));

 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h
index 5540d51..878a1ee 100644
--- a/arch/x86/include/asm/u-boot-x86.h
+++ b/arch/x86/include/asm/u-boot-x86.h
@@ -39,6 +39,7 @@  int x86_cpu_init_f(void);
 int cpu_init_f(void);
 void init_gd(gd_t *id, u64 *gdt_addr);
 void setup_gdt(gd_t *id, u64 *gdt_addr);
+int init_cache(void);

 /* cpu/.../timer.c */
 void timer_isr(void *);
diff --git a/arch/x86/lib/board.c b/arch/x86/lib/board.c
index 3d82165..56acf35 100644
--- a/arch/x86/lib/board.c
+++ b/arch/x86/lib/board.c
@@ -140,6 +140,7 @@  init_fnc_t *init_sequence_f[] = {

 init_fnc_t *init_sequence_r[] = {
 	copy_gd_to_ram,
+	init_cache,
 	cpu_init_r,		/* basic cpu dependent setup */
 	board_early_init_r,	/* basic board dependent setup */
 	dram_init,		/* configure available RAM banks */