Patchwork [v6,1/1] arm: add dummy v7 cp15 registers

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Submitter Mark Langsdorf
Date Jan. 4, 2012, 4:53 p.m.
Message ID <1325695989-4202-1-git-send-email-mark.langsdorf@calxeda.com>
Download mbox | patch
Permalink /patch/134297/
State New
Headers show

Comments

Mark Langsdorf - Jan. 4, 2012, 4:53 p.m.
Add dummy register support for the cp15, CRn=c15 registers.
config_base_register and power_control_register currently
default to 0, but may have improved support after the QOM
CPU patches are finished.

Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
---
Changes from v5
	Added handling for all c15 registers
Changes from v3, v4
        None
Changes from v2
        Added test against op2 
Changes from v1
        renamed the register
        added comments about how it will change when QOM CPUs are added

 target-arm/cpu.h    |    2 ++
 target-arm/helper.c |   30 ++++++++++++++++++++++++++++++
 2 files changed, 32 insertions(+), 0 deletions(-)
Peter Maydell - Jan. 4, 2012, 5:50 p.m.
On 4 January 2012 16:53, Mark Langsdorf <mark.langsdorf@calxeda.com> wrote:
> +        if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
> +            switch (crm) {
> +            case 0:
> +                if ((op1 == 4) && (op2 == 0)) {
> +                /* The config_base_address should hold the value of
> +                 * the peripheral base. ARM should get this from a CPU
> +                 * object property, but that support isn't available in
> +                 * December 2011. Default to 0 for now and board models
> +                 * that care can set it by a private hook */
> +                    return env->cp15.c15_config_base_address;
> +                } else if ((op1 == 0) && (op2 == 0)) {
> +                /* power_control should be set to maximum latency. Again,
> +                   default to 0 and set by private hook */
> +                    return env->cp15.c15_power_control;
> +                }

This one's read-write, which means it needs (a) support in set_cp15
(b) save/load
support.

> +                break;
> +            case 1: /* NEON Busy */
> +                return 0;
> +            case 5: /* tlb lockdown */
> +            case 6:
> +            case 7:
> +                if ((op1 == 5) && (op2 == 2)) {
> +                    return 0;
> +                }
> +                break;
> +            default:
> +                break;
> +            }
> +            goto bad_reg;
> +        }

You also need to implement the diagnostic register c15,c0,0,1
otherwise Linux won't boot when it tries to run this code:
 http://lxr.linux.no/#linux+v3.1.7/arch/arm/mm/proc-v7.S#L345
I suggest that should be implemented as reads-as-written. (Again, will
need save/load
support.) Ditto for the power diagnostic control register c15,c0,0,2, as used in
this patch: http://www.spinics.net/lists/arm-kernel/msg115817.html

-- PMM
Mark Langsdorf - Jan. 4, 2012, 6:23 p.m.
On 01/04/2012 11:50 AM, Peter Maydell wrote:
> On 4 January 2012 16:53, Mark Langsdorf <mark.langsdorf@calxeda.com> wrote:
>> +                } else if ((op1 == 0) && (op2 == 0)) {
>> +                /* power_control should be set to maximum latency. Again,
>> +                   default to 0 and set by private hook */
>> +                    return env->cp15.c15_power_control;
>> +                }
> 
> This one's read-write, which means it needs (a) support in set_cp15
> (b) save/load support.

Okay.

> You also need to implement the diagnostic register c15,c0,0,1
> otherwise Linux won't boot when it tries to run this code:
>  http://lxr.linux.no/#linux+v3.1.7/arch/arm/mm/proc-v7.S#L345
> I suggest that should be implemented as reads-as-written. (Again, will
> need save/load
> support.) Ditto for the power diagnostic control register c15,c0,0,2, as used in
> this patch: http://www.spinics.net/lists/arm-kernel/msg115817.html

I'm handling all the c15 registers listed on p 4-11 of the Cortex-A9
r3p0 TRM. Would you please give me a reference for these other two
registers? I'm not seeing them. Thanks.

--Mark

Patch

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index c4d742f..f8fb558 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -149,6 +149,8 @@  typedef struct CPUARMState {
         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
         uint32_t c15_threadid; /* TI debugger thread-ID.  */
+        uint32_t c15_config_base_address; /* SCU base address.  */
+        uint32_t c15_power_control; /* power control */
     } cp15;
 
     struct {
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 65f4fbf..f39bcf3 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2111,6 +2111,36 @@  uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
              * 0x200 << ($rn & 0xfff), when MMU is off.  */
             goto bad_reg;
         }
+        if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
+            switch (crm) {
+            case 0:
+                if ((op1 == 4) && (op2 == 0)) {
+                /* The config_base_address should hold the value of
+                 * the peripheral base. ARM should get this from a CPU
+                 * object property, but that support isn't available in
+                 * December 2011. Default to 0 for now and board models
+                 * that care can set it by a private hook */
+                    return env->cp15.c15_config_base_address;
+                } else if ((op1 == 0) && (op2 == 0)) {
+                /* power_control should be set to maximum latency. Again,
+                   default to 0 and set by private hook */
+                    return env->cp15.c15_power_control;
+                }
+                break;
+            case 1: /* NEON Busy */
+                return 0;
+            case 5: /* tlb lockdown */
+            case 6:
+            case 7:
+                if ((op1 == 5) && (op2 == 2)) {
+                    return 0;
+                }
+                break;
+            default:
+                break;
+            }
+            goto bad_reg;
+        }
         return 0;
     }
 bad_reg: