Patchwork [net-next,5/7] ixgbe: add write flush in ixgbe_clock_out_i2c_byte()

login
register
mail settings
Submitter Jeff Kirsher
Date Jan. 3, 2012, 1:50 a.m.
Message ID <1325555451-4697-6-git-send-email-jeffrey.t.kirsher@intel.com>
Download mbox | patch
Permalink /patch/133951/
State Accepted
Delegated to: David Miller
Headers show

Comments

Jeff Kirsher - Jan. 3, 2012, 1:50 a.m.
From: Emil Tantilov <emil.s.tantilov@intel.com>

I2C access is timing critical. Always do a write flush after writing
to the I2CCTL register.

Signed-off-by: Emil Tantilov <emil.s.tantilov@intel.com>
Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
---
 drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

Patch

diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c
index 8b113e3..7cf1e1f 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c
@@ -1457,6 +1457,7 @@  static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
 	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
 	i2cctl |= IXGBE_I2C_DATA_OUT;
 	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
+	IXGBE_WRITE_FLUSH(hw);
 
 	return status;
 }