From patchwork Sat Dec 31 04:54:51 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 133727 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 00FACB6FC9 for ; Sat, 31 Dec 2011 15:56:45 +1100 (EST) Received: from localhost ([::1]:55474 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rgqzq-0000Sk-0M for incoming@patchwork.ozlabs.org; Fri, 30 Dec 2011 23:56:42 -0500 Received: from eggs.gnu.org ([140.186.70.92]:52068) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RgqzY-0000HZ-S2 for qemu-devel@nongnu.org; Fri, 30 Dec 2011 23:56:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RgqzX-0000g1-4p for qemu-devel@nongnu.org; Fri, 30 Dec 2011 23:56:24 -0500 Received: from mail-yx0-f173.google.com ([209.85.213.173]:56014) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RgqzW-0000fv-Nq for qemu-devel@nongnu.org; Fri, 30 Dec 2011 23:56:22 -0500 Received: by yenm6 with SMTP id m6so9497769yen.4 for ; Fri, 30 Dec 2011 20:56:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=+L+xNMikgdKXLNe7FUq+hudPu/MR68L/O1F0yuUdpvY=; b=wK6rjssrvTSJj8ZQ7m8gCO165f1UL70S0vqCTK1VQVp/4SC4CGOe2Ilv/iCxJ6f9hD k3/uvggsASo2kKr49y9DVog8VKFVGt0DYxE2IZuxhubQ4IrH40XDVjE3PLY2VoT5wKWZ /oyNd3TIYJ9nTnwXxEmV4BdhPKKfECecTGyAE= Received: by 10.236.121.168 with SMTP id r28mr42843981yhh.18.1325307382228; Fri, 30 Dec 2011 20:56:22 -0800 (PST) Received: from pebble.com ([101.172.149.215]) by mx.google.com with ESMTPS id v8sm11097049yhi.10.2011.12.30.20.56.19 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 30 Dec 2011 20:56:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 31 Dec 2011 15:54:51 +1100 Message-Id: <1325307291-6334-4-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.7.4 In-Reply-To: <1325307291-6334-1-git-send-email-rth@twiddle.net> References: <1325307291-6334-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.213.173 Cc: peter.maydell@linaro.org, afaerber@suse.de, Aurelien Jarno Subject: [Qemu-devel] [PATCH 4/4] target-mips: Fix MIPS_DEBUG. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The macro uses the DisasContext. Pass it around as needed. Signed-off-by: Richard Henderson --- target-mips/translate.c | 80 ++++++++++++++++++++++++++--------------------- 1 files changed, 44 insertions(+), 36 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 8908c8c..11272b6 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1489,7 +1489,8 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc, } /* Logic with immediate operand */ -static void gen_logic_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t imm) +static void gen_logic_imm (CPUState *env, DisasContext *ctx, uint32_t opc, + int rt, int rs, int16_t imm) { target_ulong uimm; const char *opn = "imm logic"; @@ -1532,7 +1533,8 @@ static void gen_logic_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t } /* Set on less than with immediate operand */ -static void gen_slt_imm (CPUState *env, uint32_t opc, int rt, int rs, int16_t imm) +static void gen_slt_imm (CPUState *env, DisasContext *ctx, uint32_t opc, + int rt, int rs, int16_t imm) { target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */ const char *opn = "imm arith"; @@ -1833,7 +1835,8 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc, } /* Conditional move */ -static void gen_cond_move (CPUState *env, uint32_t opc, int rd, int rs, int rt) +static void gen_cond_move (CPUState *env, DisasContext *ctx, uint32_t opc, + int rd, int rs, int rt) { const char *opn = "cond move"; int l1; @@ -1871,7 +1874,8 @@ static void gen_cond_move (CPUState *env, uint32_t opc, int rd, int rs, int rt) } /* Logic */ -static void gen_logic (CPUState *env, uint32_t opc, int rd, int rs, int rt) +static void gen_logic (CPUState *env, DisasContext *ctx, uint32_t opc, + int rd, int rs, int rt) { const char *opn = "logic"; @@ -1932,7 +1936,8 @@ static void gen_logic (CPUState *env, uint32_t opc, int rd, int rs, int rt) } /* Set on lower than */ -static void gen_slt (CPUState *env, uint32_t opc, int rd, int rs, int rt) +static void gen_slt (CPUState *env, DisasContext *ctx, uint32_t opc, + int rd, int rs, int rt) { const char *opn = "slt"; TCGv t0, t1; @@ -8823,10 +8828,10 @@ static int decode_extended_mips16_opc (CPUState *env, DisasContext *ctx, gen_arith_imm(env, ctx, OPC_ADDIU, rx, rx, imm); break; case M16_OPC_SLTI: - gen_slt_imm(env, OPC_SLTI, 24, rx, imm); + gen_slt_imm(env, ctx, OPC_SLTI, 24, rx, imm); break; case M16_OPC_SLTIU: - gen_slt_imm(env, OPC_SLTIU, 24, rx, imm); + gen_slt_imm(env, ctx, OPC_SLTIU, 24, rx, imm); break; case M16_OPC_I8: switch (funct) { @@ -9037,15 +9042,13 @@ static int decode_mips16_opc (CPUState *env, DisasContext *ctx, case M16_OPC_SLTI: { int16_t imm = (uint8_t) ctx->opcode; - - gen_slt_imm(env, OPC_SLTI, 24, rx, imm); + gen_slt_imm(env, ctx, OPC_SLTI, 24, rx, imm); } break; case M16_OPC_SLTIU: { int16_t imm = (uint8_t) ctx->opcode; - - gen_slt_imm(env, OPC_SLTIU, 24, rx, imm); + gen_slt_imm(env, ctx, OPC_SLTIU, 24, rx, imm); } break; case M16_OPC_I8: @@ -9120,8 +9123,7 @@ static int decode_mips16_opc (CPUState *env, DisasContext *ctx, case M16_OPC_CMPI: { int16_t imm = (uint8_t) ctx->opcode; - - gen_logic_imm(env, OPC_XORI, 24, rx, imm); + gen_logic_imm(env, ctx, OPC_XORI, 24, rx, imm); } break; #if defined(TARGET_MIPS64) @@ -9233,10 +9235,10 @@ static int decode_mips16_opc (CPUState *env, DisasContext *ctx, } break; case RR_SLT: - gen_slt(env, OPC_SLT, 24, rx, ry); + gen_slt(env, ctx, OPC_SLT, 24, rx, ry); break; case RR_SLTU: - gen_slt(env, OPC_SLTU, 24, rx, ry); + gen_slt(env, ctx, OPC_SLTU, 24, rx, ry); break; case RR_BREAK: generate_exception(ctx, EXCP_BREAK); @@ -9257,22 +9259,22 @@ static int decode_mips16_opc (CPUState *env, DisasContext *ctx, break; #endif case RR_CMP: - gen_logic(env, OPC_XOR, 24, rx, ry); + gen_logic(env, ctx, OPC_XOR, 24, rx, ry); break; case RR_NEG: gen_arith(env, ctx, OPC_SUBU, rx, 0, ry); break; case RR_AND: - gen_logic(env, OPC_AND, rx, rx, ry); + gen_logic(env, ctx, OPC_AND, rx, rx, ry); break; case RR_OR: - gen_logic(env, OPC_OR, rx, rx, ry); + gen_logic(env, ctx, OPC_OR, rx, rx, ry); break; case RR_XOR: - gen_logic(env, OPC_XOR, rx, rx, ry); + gen_logic(env, ctx, OPC_XOR, rx, rx, ry); break; case RR_NOT: - gen_logic(env, OPC_NOR, rx, ry, 0); + gen_logic(env, ctx, OPC_NOR, rx, ry, 0); break; case RR_MFHI: gen_HILO(ctx, OPC_MFHI, rx); @@ -9894,12 +9896,13 @@ static void gen_andi16 (CPUState *env, DisasContext *ctx) int rs = mmreg(uMIPS_RS(ctx->opcode)); int encoded = ZIMM(ctx->opcode, 0, 4); - gen_logic_imm(env, OPC_ANDI, rd, rs, decoded_imm[encoded]); + gen_logic_imm(env, ctx, OPC_ANDI, rd, rs, decoded_imm[encoded]); } static void gen_ldst_multiple (DisasContext *ctx, uint32_t opc, int reglist, int base, int16_t offset) { + const char *opn = "ldst_multiple"; TCGv t0, t1; TCGv_i32 t2; @@ -9919,19 +9922,24 @@ static void gen_ldst_multiple (DisasContext *ctx, uint32_t opc, int reglist, switch (opc) { case LWM32: gen_helper_lwm(t0, t1, t2); + opn = "lwm"; break; case SWM32: gen_helper_swm(t0, t1, t2); + opn = "swm"; break; #ifdef TARGET_MIPS64 case LDM: gen_helper_ldm(t0, t1, t2); + opn = "ldm"; break; case SDM: gen_helper_sdm(t0, t1, t2); + opn = "sdm"; break; #endif } + (void)opn; MIPS_DEBUG("%s, %x, %d(%s)", opn, reglist, offset, regnames[base]); tcg_temp_free(t0); tcg_temp_free(t1); @@ -9950,25 +9958,25 @@ static void gen_pool16c_insn (CPUState *env, DisasContext *ctx, int *is_branch) case NOT16 + 1: case NOT16 + 2: case NOT16 + 3: - gen_logic(env, OPC_NOR, rd, rs, 0); + gen_logic(env, ctx, OPC_NOR, rd, rs, 0); break; case XOR16 + 0: case XOR16 + 1: case XOR16 + 2: case XOR16 + 3: - gen_logic(env, OPC_XOR, rd, rd, rs); + gen_logic(env, ctx, OPC_XOR, rd, rd, rs); break; case AND16 + 0: case AND16 + 1: case AND16 + 2: case AND16 + 3: - gen_logic(env, OPC_AND, rd, rd, rs); + gen_logic(env, ctx, OPC_AND, rd, rd, rs); break; case OR16 + 0: case OR16 + 1: case OR16 + 2: case OR16 + 3: - gen_logic(env, OPC_OR, rd, rd, rs); + gen_logic(env, ctx, OPC_OR, rd, rd, rs); break; case LWM16 + 0: case LWM16 + 1: @@ -10768,7 +10776,7 @@ static void decode_micromips32_opc (CPUState *env, DisasContext *ctx, case XOR32: mips32_op = OPC_XOR; do_logic: - gen_logic(env, mips32_op, rd, rs, rt); + gen_logic(env, ctx, mips32_op, rd, rs, rt); break; /* Set less than */ case SLT: @@ -10777,7 +10785,7 @@ static void decode_micromips32_opc (CPUState *env, DisasContext *ctx, case SLTU: mips32_op = OPC_SLTU; do_slt: - gen_slt(env, mips32_op, rd, rs, rt); + gen_slt(env, ctx, mips32_op, rd, rs, rt); break; default: goto pool32a_invalid; @@ -10793,7 +10801,7 @@ static void decode_micromips32_opc (CPUState *env, DisasContext *ctx, case MOVZ: mips32_op = OPC_MOVZ; do_cmov: - gen_cond_move(env, mips32_op, rd, rs, rt); + gen_cond_move(env, ctx, mips32_op, rd, rs, rt); break; case LWXS: gen_ldxs(ctx, rs, rt, rd); @@ -11205,7 +11213,7 @@ static void decode_micromips32_opc (CPUState *env, DisasContext *ctx, target. */ break; case LUI: - gen_logic_imm(env, OPC_LUI, rs, -1, imm); + gen_logic_imm(env, ctx, OPC_LUI, rs, -1, imm); break; case SYNCI: break; @@ -11324,7 +11332,7 @@ static void decode_micromips32_opc (CPUState *env, DisasContext *ctx, case ANDI32: mips32_op = OPC_ANDI; do_logici: - gen_logic_imm(env, mips32_op, rt, rs, imm); + gen_logic_imm(env, ctx, mips32_op, rt, rs, imm); break; /* Set less than immediate */ @@ -11334,7 +11342,7 @@ static void decode_micromips32_opc (CPUState *env, DisasContext *ctx, case SLTIU32: mips32_op = OPC_SLTIU; do_slti: - gen_slt_imm(env, mips32_op, rt, rs, imm); + gen_slt_imm(env, ctx, mips32_op, rt, rs, imm); break; case JALX32: offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; @@ -11811,7 +11819,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx, int *is_branch) case OPC_MOVZ: check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32 | INSN_LOONGSON2E | INSN_LOONGSON2F); - gen_cond_move(env, op1, rd, rs, rt); + gen_cond_move(env, ctx, op1, rd, rs, rt); break; case OPC_ADD ... OPC_SUBU: gen_arith(env, ctx, op1, rd, rs, rt); @@ -11838,13 +11846,13 @@ static void decode_opc (CPUState *env, DisasContext *ctx, int *is_branch) break; case OPC_SLT: /* Set on less than */ case OPC_SLTU: - gen_slt(env, op1, rd, rs, rt); + gen_slt(env, ctx, op1, rd, rs, rt); break; case OPC_AND: /* Logic*/ case OPC_OR: case OPC_NOR: case OPC_XOR: - gen_logic(env, op1, rd, rs, rt); + gen_logic(env, ctx, op1, rd, rs, rt); break; case OPC_MULT ... OPC_DIVU: if (sa) { @@ -12245,13 +12253,13 @@ static void decode_opc (CPUState *env, DisasContext *ctx, int *is_branch) break; case OPC_SLTI: /* Set on less than with immediate opcode */ case OPC_SLTIU: - gen_slt_imm(env, op, rt, rs, imm); + gen_slt_imm(env, ctx, op, rt, rs, imm); break; case OPC_ANDI: /* Arithmetic with immediate opcode */ case OPC_LUI: case OPC_ORI: case OPC_XORI: - gen_logic_imm(env, op, rt, rs, imm); + gen_logic_imm(env, ctx, op, rt, rs, imm); break; case OPC_J ... OPC_JAL: /* Jump */ offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;