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[RFC,ARM,3/5] Adjust the maximum number of if-converted insns to 4

Message ID 4EFDEB6A.8000900@ispras.ru
State New
Headers show

Commit Message

Dmitry Melnik Dec. 30, 2011, 4:48 p.m. UTC 
This patch adjusts the maximum number of instructions in a basic block 
to be converted into conditional form from 5 to 4. The idea is that the 
5-th conditional instruction comes at cost of extra IT-instruction, 
while 4 insns fit into single IT-block, so this IT-instruction replaces 
eliminated branch insn and code won't grow. This limit is applied for 
each of converted conditional branches.
This reduces code size by 96 bytes on SPEC2K INT with -O2 (with +4 byte 
regression on one test).
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Patch

2011-12-29  Dmitry Melnik <dm@ispras.ru> 

gcc/
    * config/arm/arm.h (MAX_CONDITIONAL_EXECUTE): New macro.

diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 85e2b99..acad3ec 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1990,6 +1990,15 @@  typedef struct
 #define BRANCH_COST(speed_p, predictable_p) \
   (current_tune->branch_cost (speed_p, predictable_p))
 
+/* One IT-block consists of 4 insns at maximum.  If-conversion can eliminate
+   2 branches for IFs with both THEN and ELSE branches, and 1 branch for
+   those with only THEN branch.  If we don't want code size to grow, and just
+   allow trading branch insns for IT insns, we should limit number of converted
+   insns to 4 (and in ifcvt.c it will be doubled if there are 2 branches).  */
+#define MAX_CONDITIONAL_EXECUTE                                             \
+  ((TARGET_THUMB2) ? 4 : BRANCH_COST (optimize_function_for_speed_p (cfun), \
+                                      false) + 1)
+
 
 /* Position Independent Code.  */
 /* We decide which register to use based on the compilation options and