From patchwork Fri Dec 30 09:26:40 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: ARM: imx6: fix v7_invalidate_l1 by adding I-Cache invalidation Date: Thu, 29 Dec 2011 23:26:40 -0000 From: Shawn Guo X-Patchwork-Id: 133623 Message-Id: <1325237200-10610-1-git-send-email-shawn.guo@linaro.org> To: linux-arm-kernel@lists.infradead.org Cc: Shawn Guo , patches@linaro.org The recent suspend/resume and reset testing on imx6q discovers that not only D-Cache but also I-Cache has random data and validity when the core comes out of a power recycle. This patch adds I-Cache invalidation into v7_invalidate_l1 to make sure both D-Cache and I-Cache invalidated on power-up. Signed-off-by: Shawn Guo Reviewed-by: Kyungmin Park --- arch/arm/mach-imx/head-v7.S | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-imx/head-v7.S b/arch/arm/mach-imx/head-v7.S index 6229efb..c844112 100644 --- a/arch/arm/mach-imx/head-v7.S +++ b/arch/arm/mach-imx/head-v7.S @@ -33,6 +33,7 @@ */ ENTRY(v7_invalidate_l1) mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache mcr p15, 2, r0, c0, c0, 0 mrc p15, 1, r0, c0, c0, 0