From patchwork Thu Dec 29 16:19:52 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Langsdorf X-Patchwork-Id: 133570 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B9D9FB6FB7 for ; Fri, 30 Dec 2011 03:20:26 +1100 (EST) Received: from localhost ([::1]:57420 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RgIiN-0005Lm-ID for incoming@patchwork.ozlabs.org; Thu, 29 Dec 2011 11:20:23 -0500 Received: from eggs.gnu.org ([140.186.70.92]:49825) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RgIi5-0005EZ-7w for qemu-devel@nongnu.org; Thu, 29 Dec 2011 11:20:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RgIi2-0007ma-JS for qemu-devel@nongnu.org; Thu, 29 Dec 2011 11:20:04 -0500 Received: from smtp151.dfw.emailsrvr.com ([67.192.241.151]:49866) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RgIi2-0007mP-D0 for qemu-devel@nongnu.org; Thu, 29 Dec 2011 11:20:02 -0500 Received: from localhost (localhost.localdomain [127.0.0.1]) by smtp5.relay.dfw1a.emailsrvr.com (SMTP Server) with ESMTP id 87612585C5; Thu, 29 Dec 2011 11:20:00 -0500 (EST) X-Virus-Scanned: OK Received: by smtp5.relay.dfw1a.emailsrvr.com (Authenticated sender: mark.langsdorf-AT-calxeda.com) with ESMTPSA id 5099C5835C; Thu, 29 Dec 2011 11:20:00 -0500 (EST) From: Mark Langsdorf To: qemu-devel@nongnu.org Date: Thu, 29 Dec 2011 10:19:52 -0600 Message-Id: <1325175596-5807-4-git-send-email-mark.langsdorf@calxeda.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1325175596-5807-1-git-send-email-mark.langsdorf@calxeda.com> References: <1325175596-5807-1-git-send-email-mark.langsdorf@calxeda.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 67.192.241.151 Cc: peter.maydell@linaro.org, Mark Langsdorf , afaerber@suse.de, rob.herring@calxeda.com Subject: [Qemu-devel] [PATCH v5 3/7] arm: add dummy v7 cp15 config_base_register X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add a cp15 config_base_register that currently defaults to 0. After the QOM CPU support is added, the value will be properly set to the periphal base value. Signed-off-by: Mark Langsdorf Reviewed-by: Peter Maydell --- Changes from v3, v4 None Changes from v2 Added test against op2 Changes from v1 renamed the register added comments about how it will change when QOM CPUs are added target-arm/cpu.h | 1 + target-arm/helper.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+), 0 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index c4d742f..449e620 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -149,6 +149,7 @@ typedef struct CPUARMState { uint32_t c15_i_max; /* Maximum D-cache dirty line index. */ uint32_t c15_i_min; /* Minimum D-cache dirty line index. */ uint32_t c15_threadid; /* TI debugger thread-ID. */ + uint32_t c15_config_base_address; /* SCU base address. */ } cp15; struct { diff --git a/target-arm/helper.c b/target-arm/helper.c index 65f4fbf..b235fed 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2111,6 +2111,20 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) * 0x200 << ($rn & 0xfff), when MMU is off. */ goto bad_reg; } + if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) { + switch (crm) { + case 0: + /* The config_base_address should hold the value of + * the peripheral base. ARM should get this from a CPU + * object property, but that support isn't available in + * December 2011. Default to 0 for now and board models + * that care can set it by a private hook */ + if ((op1 == 4) && (op2 == 0)) { + return env->cp15.c15_config_base_address; + } + } + goto bad_reg; + } return 0; } bad_reg: