Patchwork [v5,3/7] arm: add dummy v7 cp15 config_base_register

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Submitter Mark Langsdorf
Date Dec. 29, 2011, 4:19 p.m.
Message ID <1325175596-5807-4-git-send-email-mark.langsdorf@calxeda.com>
Download mbox | patch
Permalink /patch/133570/
State New
Headers show

Comments

Mark Langsdorf - Dec. 29, 2011, 4:19 p.m.
Add a cp15 config_base_register that currently defaults to 0.
After the QOM CPU support is added, the value will be properly
set to the periphal base value.

Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
Changes from v3, v4
	None
Changes from v2
        Added test against op2 
Changes from v1
        renamed the register
        added comments about how it will change when QOM CPUs are added

 target-arm/cpu.h    |    1 +
 target-arm/helper.c |   14 ++++++++++++++
 2 files changed, 15 insertions(+), 0 deletions(-)
Peter Maydell - Jan. 4, 2012, 2:32 p.m.
On 29 December 2011 16:19, Mark Langsdorf <mark.langsdorf@calxeda.com> wrote:
> Add a cp15 config_base_register that currently defaults to 0.
> After the QOM CPU support is added, the value will be properly
> set to the periphal base value.
>
> Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

I need to revoke this Reviewed-by: because...

> @@ -2111,6 +2111,20 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
>              * 0x200 << ($rn & 0xfff), when MMU is off.  */
>             goto bad_reg;
>         }
> +        if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
> +            switch (crm) {
> +            case 0:
> +                /* The config_base_address should hold the value of
> +                 * the peripheral base. ARM should get this from a CPU
> +                 * object property, but that support isn't available in
> +                 * December 2011. Default to 0 for now and board models
> +                 * that care can set it by a private hook */
> +                if ((op1 == 4) && (op2 == 0)) {
> +                    return env->cp15.c15_config_base_address;
> +                }
> +            }
> +            goto bad_reg;
> +        }
>         return 0;

this breaks booting on vexpress, which complains
qemu: fatal: Unimplemented cp15 register read (c15, c0, {0, 1})
because we're now barfing on all the other c15 registers which we
used to read as zero.

The simplest fix is to drop that 'goto bad_reg;'.
More complicatedly we could decode the c15 range properly for A9
(as per the TRM).

-- PMM
Mark Langsdorf - Jan. 4, 2012, 4:32 p.m.
On 01/04/2012 08:32 AM, Peter Maydell wrote:
> On 29 December 2011 16:19, Mark Langsdorf <mark.langsdorf@calxeda.com> wrote:
>> Add a cp15 config_base_register that currently defaults to 0.
>> After the QOM CPU support is added, the value will be properly
>> set to the periphal base value.
>>
>> Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
>> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> 
> I need to revoke this Reviewed-by: because...
> 
>> @@ -2111,6 +2111,20 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
>>              * 0x200 << ($rn & 0xfff), when MMU is off.  */
>>             goto bad_reg;
>>         }
>> +        if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
>> +            switch (crm) {
>> +            case 0:
>> +                /* The config_base_address should hold the value of
>> +                 * the peripheral base. ARM should get this from a CPU
>> +                 * object property, but that support isn't available in
>> +                 * December 2011. Default to 0 for now and board models
>> +                 * that care can set it by a private hook */
>> +                if ((op1 == 4) && (op2 == 0)) {
>> +                    return env->cp15.c15_config_base_address;
>> +                }
>> +            }
>> +            goto bad_reg;
>> +        }
>>         return 0;
> 
> this breaks booting on vexpress, which complains
> qemu: fatal: Unimplemented cp15 register read (c15, c0, {0, 1})
> because we're now barfing on all the other c15 registers which we
> used to read as zero.

Fair enough. Can I just resubmit this one patch or do you want
the entire series?

--Mark Langsdorf
Calxeda, Inc.
Peter Maydell - Jan. 4, 2012, 4:47 p.m.
On 4 January 2012 16:32, Mark Langsdorf <mark.langsdorf@calxeda.com> wrote:
> On 01/04/2012 08:32 AM, Peter Maydell wrote:
>> On 29 December 2011 16:19, Mark Langsdorf <mark.langsdorf@calxeda.com> wrote:
>>> Add a cp15 config_base_register that currently defaults to 0.
>>> After the QOM CPU support is added, the value will be properly
>>> set to the periphal base value.
>>>
>>> Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
>>> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
>>
>> I need to revoke this Reviewed-by: because...
>>
>>> @@ -2111,6 +2111,20 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
>>>              * 0x200 << ($rn & 0xfff), when MMU is off.  */
>>>             goto bad_reg;
>>>         }
>>> +        if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
>>> +            switch (crm) {
>>> +            case 0:
>>> +                /* The config_base_address should hold the value of
>>> +                 * the peripheral base. ARM should get this from a CPU
>>> +                 * object property, but that support isn't available in
>>> +                 * December 2011. Default to 0 for now and board models
>>> +                 * that care can set it by a private hook */
>>> +                if ((op1 == 4) && (op2 == 0)) {
>>> +                    return env->cp15.c15_config_base_address;
>>> +                }
>>> +            }
>>> +            goto bad_reg;
>>> +        }
>>>         return 0;
>>
>> this breaks booting on vexpress, which complains
>> qemu: fatal: Unimplemented cp15 register read (c15, c0, {0, 1})
>> because we're now barfing on all the other c15 registers which we
>> used to read as zero.
>
> Fair enough. Can I just resubmit this one patch or do you want
> the entire series?

Just resubmit this one as a single patch -- it has to go through my target-arm
tree rather than arm-devs anyway so if you resent the series I'd just have
to break it apart. (As you may have noticed I've put some of the other
patches into an arm-devs pullreq.)

-- PMM

Patch

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index c4d742f..449e620 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -149,6 +149,7 @@  typedef struct CPUARMState {
         uint32_t c15_i_max; /* Maximum D-cache dirty line index.  */
         uint32_t c15_i_min; /* Minimum D-cache dirty line index.  */
         uint32_t c15_threadid; /* TI debugger thread-ID.  */
+        uint32_t c15_config_base_address; /* SCU base address.  */
     } cp15;
 
     struct {
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 65f4fbf..b235fed 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2111,6 +2111,20 @@  uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
              * 0x200 << ($rn & 0xfff), when MMU is off.  */
             goto bad_reg;
         }
+        if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
+            switch (crm) {
+            case 0:
+                /* The config_base_address should hold the value of
+                 * the peripheral base. ARM should get this from a CPU
+                 * object property, but that support isn't available in
+                 * December 2011. Default to 0 for now and board models
+                 * that care can set it by a private hook */
+                if ((op1 == 4) && (op2 == 0)) {
+                    return env->cp15.c15_config_base_address;
+                }
+            }
+            goto bad_reg;
+        }
         return 0;
     }
 bad_reg: