From patchwork Tue Dec 27 20:13:39 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Langsdorf X-Patchwork-Id: 133362 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3A749B6FA5 for ; Wed, 28 Dec 2011 07:57:04 +1100 (EST) Received: from localhost ([::1]:53298 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RfdPt-0002tC-2f for incoming@patchwork.ozlabs.org; Tue, 27 Dec 2011 15:14:33 -0500 Received: from eggs.gnu.org ([140.186.70.92]:51928) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RfdP2-00014b-En for qemu-devel@nongnu.org; Tue, 27 Dec 2011 15:13:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RfdP1-0000JH-7j for qemu-devel@nongnu.org; Tue, 27 Dec 2011 15:13:40 -0500 Received: from smtp131.dfw.emailsrvr.com ([67.192.241.131]:54651) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RfdP1-0000Fk-38 for qemu-devel@nongnu.org; Tue, 27 Dec 2011 15:13:39 -0500 Received: from localhost (localhost.localdomain [127.0.0.1]) by smtp23.relay.dfw1a.emailsrvr.com (SMTP Server) with ESMTP id BED072F83F6; Tue, 27 Dec 2011 15:13:37 -0500 (EST) X-Virus-Scanned: OK Received: by smtp23.relay.dfw1a.emailsrvr.com (Authenticated sender: mark.langsdorf-AT-calxeda.com) with ESMTPSA id 8ED682F83CF; Tue, 27 Dec 2011 15:13:37 -0500 (EST) From: Mark Langsdorf To: qemu-devel@nongnu.org Date: Tue, 27 Dec 2011 14:13:39 -0600 Message-Id: <1325016827-11503-2-git-send-email-mark.langsdorf@calxeda.com> X-Mailer: git-send-email 1.7.5.4 In-Reply-To: <1325016827-11503-1-git-send-email-mark.langsdorf@calxeda.com> References: <1325016827-11503-1-git-send-email-mark.langsdorf@calxeda.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 67.192.241.131 Cc: kwolf@redhat.com, peter.maydell@linaro.org, Mark Langsdorf , paul@codesourcery.com, rob.herring@calxeda.com Subject: [Qemu-devel] [PATCH v3 1/9] arm: add missing scu registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Rob Herring Add power control register to a9mpcore Signed-off-by: Rob Herring Signed-off-by: Mark Langsdorf Reviewed-by: Peter Maydell --- Changes from v2: Better handling of byte and halfword writes to the power register Correct handling of VMState versions Improved commit message Changes from v1: Added VMState support Checked alignment of writes to the power control register hw/a9mpcore.c | 36 +++++++++++++++++++++++++++++++++--- 1 files changed, 33 insertions(+), 3 deletions(-) diff --git a/hw/a9mpcore.c b/hw/a9mpcore.c index cd2985f..3ef0e13 100644 --- a/hw/a9mpcore.c +++ b/hw/a9mpcore.c @@ -29,6 +29,7 @@ gic_get_current_cpu(void) typedef struct a9mp_priv_state { gic_state gic; uint32_t scu_control; + uint32_t scu_status; uint32_t old_timer_status[8]; uint32_t num_cpu; qemu_irq *timer_irq; @@ -48,7 +49,13 @@ static uint64_t a9_scu_read(void *opaque, target_phys_addr_t offset, case 0x04: /* Configuration */ return (((1 << s->num_cpu) - 1) << 4) | (s->num_cpu - 1); case 0x08: /* CPU Power Status */ - return 0; + return s->scu_status; + case 0x09: /* CPU status. */ + return s->scu_status >> 8; + case 0x0a: /* CPU status. */ + return s->scu_status >> 16; + case 0x0b: /* CPU status. */ + return s->scu_status >> 24; case 0x0c: /* Invalidate All Registers In Secure State */ return 0; case 0x40: /* Filtering Start Address Register */ @@ -67,12 +74,35 @@ static void a9_scu_write(void *opaque, target_phys_addr_t offset, uint64_t value, unsigned size) { a9mp_priv_state *s = (a9mp_priv_state *)opaque; + uint32_t mask; + uint32_t shift; + switch (size) { + case 1: + mask = 0xff; + break; + case 2: + mask = 0xffff; + break; + case 4: + mask = 0xffffffff; + break; + default: + fprintf(stderr, "Invalid size %u in write to a9 scu register %x\n", + size, offset); + return; + } + switch (offset) { case 0x00: /* Control */ s->scu_control = value & 1; break; case 0x4: /* Configuration: RO */ break; + case 0x08: case 0x09: case 0x0A: case 0x0B: /* Power Control */ + shift = (offset - 0x8) * 8; + s->scu_status &= ~(mask << shift); + s->scu_status |= ((value & mask) << shift); + break; case 0x0c: /* Invalidate All Registers In Secure State */ /* no-op as we do not implement caches */ break; @@ -80,7 +110,6 @@ static void a9_scu_write(void *opaque, target_phys_addr_t offset, case 0x44: /* Filtering End Address Register */ /* RAZ/WI, like an implementation with only one AXI master */ break; - case 0x8: /* CPU Power Status */ case 0x50: /* SCU Access Control Register */ case 0x54: /* SCU Non-secure Access Control Register */ /* unimplemented, fall through */ @@ -169,11 +198,12 @@ static int a9mp_priv_init(SysBusDevice *dev) static const VMStateDescription vmstate_a9mp_priv = { .name = "a9mpcore_priv", - .version_id = 1, + .version_id = 2, .minimum_version_id = 1, .fields = (VMStateField[]) { VMSTATE_UINT32(scu_control, a9mp_priv_state), VMSTATE_UINT32_ARRAY(old_timer_status, a9mp_priv_state, 8), + VMSTATE_UINT32_V(scu_status, a9mp_priv_state, 2), VMSTATE_END_OF_LIST() } };