From patchwork Thu Dec 22 22:26:17 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Scott Wood X-Patchwork-Id: 132915 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 9F91EB71B8 for ; Fri, 23 Dec 2011 09:26:39 +1100 (EST) Received: from localhost ([::1]:47919 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rdr5v-0005yn-5o for incoming@patchwork.ozlabs.org; Thu, 22 Dec 2011 17:26:35 -0500 Received: from eggs.gnu.org ([140.186.70.92]:38297) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rdr5o-0005y6-TP for qemu-devel@nongnu.org; Thu, 22 Dec 2011 17:26:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rdr5n-00040U-Gm for qemu-devel@nongnu.org; Thu, 22 Dec 2011 17:26:28 -0500 Received: from va3ehsobe006.messaging.microsoft.com ([216.32.180.16]:46643 helo=VA3EHSOBE007.bigfish.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rdr5l-00040B-8U; Thu, 22 Dec 2011 17:26:25 -0500 Received: from mail59-va3-R.bigfish.com (10.7.14.244) by VA3EHSOBE007.bigfish.com (10.7.40.11) with Microsoft SMTP Server id 14.1.225.23; Thu, 22 Dec 2011 22:26:11 +0000 Received: from mail59-va3 (localhost [127.0.0.1]) by mail59-va3-R.bigfish.com (Postfix) with ESMTP id EB21C3404A3; Thu, 22 Dec 2011 22:25:50 +0000 (UTC) X-SpamScore: 3 X-BigFish: VS3(zzc8kzz1202hzz8275bhz2dh2a8h668h839h944h) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail59-va3 (localhost.localdomain [127.0.0.1]) by mail59-va3 (MessageSwitch) id 1324592748200177_2881; Thu, 22 Dec 2011 22:25:48 +0000 (UTC) Received: from VA3EHSMHS022.bigfish.com (unknown [10.7.14.237]) by mail59-va3.bigfish.com (Postfix) with ESMTP id 1C93C66003F; Thu, 22 Dec 2011 22:25:48 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS022.bigfish.com (10.7.99.32) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 22 Dec 2011 22:26:08 +0000 Received: from az33smr02.freescale.net (10.64.34.200) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.355.3; Thu, 22 Dec 2011 16:26:19 -0600 Received: from schlenkerla.am.freescale.net (schlenkerla.am.freescale.net [10.82.121.12]) by az33smr02.freescale.net (8.13.1/8.13.0) with ESMTP id pBMMQHH3008529; Thu, 22 Dec 2011 16:26:18 -0600 (CST) Date: Thu, 22 Dec 2011 16:26:17 -0600 From: Scott Wood To: Message-ID: <20111222222617.GA21119@schlenkerla.am.freescale.net> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-OriginatorOrg: freescale.com X-detected-operating-system: by eggs.gnu.org: Windows XP/2000 (RFC1323+, w+, tstamp-) X-Received-From: 216.32.180.16 Cc: varun.sethi@freescale.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH] PPC: Add description for the Freescale e500mc core. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Varun Sethi This core is found on chips such as p4080, p3041, p2040, and p5020. More needs to be done to make this viable for TCG (such as missing SPRs and instructions), but this suffices to get KVM running with appropriate kernel support. Signed-off-by: Varun Sethi [scottwood@freescale.com: tweak some flags] Signed-off-by: Scott Wood --- Kernel support for e500mc KVM was recently posted as an RFC patchset. For now, use the mpc8544ds platform, pass "-cpu e500mc", and edit the device tree to have a top-level compatible that Linux will accept (such as fsl,P4080DS). target-ppc/translate_init.c | 56 ++++++++++++++++++++++++++++++++++++++---- 1 files changed, 50 insertions(+), 6 deletions(-) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 8a7233f..e312121 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -2,6 +2,7 @@ * PowerPC CPU initialization for qemu. * * Copyright (c) 2003-2007 Jocelyn Mayer + * Copyright 2011 Freescale Semiconductor, Inc. * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public @@ -4399,6 +4400,33 @@ static void init_proc_e300 (CPUPPCState *env) #define check_pow_e500v2 check_pow_hid0 #define init_proc_e500v2 init_proc_e500v2 +/* e500mc core */ +#define POWERPC_INSNS_e500mc (PPC_INSNS_BASE | PPC_ISEL | \ + PPC_WRTEE | PPC_RFDI | PPC_RFMCI | \ + PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | \ + PPC_CACHE_DCBZ | PPC_CACHE_DCBA | \ + PPC_FLOAT | PPC_FLOAT_FRES | \ + PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | \ + PPC_FLOAT_STFIWX | PPC_WAIT | \ + PPC_MEM_TLBSYNC | PPC_TLBIVAX) +#define POWERPC_INSNS2_e500mc (PPC2_BOOKE206) +#define POWERPC_MSRM_e500mc (0x000000001402FB36ULL) +#define POWERPC_MMU_e500mc (POWERPC_MMU_BOOKE206) +#define POWERPC_EXCP_e500mc (POWERPC_EXCP_BOOKE) +#define POWERPC_INPUT_e500mc (PPC_FLAGS_INPUT_BookE) +/* Fixme: figure out the correct flag for e500mc */ +#define POWERPC_BFDM_e500mc (bfd_mach_ppc_e500) +#define POWERPC_FLAG_e500mc (POWERPC_FLAG_CE | POWERPC_FLAG_DE | \ + POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK) +#define check_pow_e500mc check_pow_none +#define init_proc_e500mc init_proc_e500mc + +enum fsl_e500_version { + fsl_e500v1, + fsl_e500v2, + fsl_e500mc, +}; + static void init_proc_e500 (CPUPPCState *env, int version) { uint32_t tlbncfg[2]; @@ -4430,15 +4458,26 @@ static void init_proc_e500 (CPUPPCState *env, int version) env->nb_ways = 2; env->id_tlbs = 0; switch (version) { - case 1: + case fsl_e500v1: /* e500v1 */ tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256); tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); + env->dcache_line_size = 32; + env->icache_line_size = 32; break; - case 2: + case fsl_e500v2: /* e500v2 */ tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512); tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); + env->dcache_line_size = 32; + env->icache_line_size = 32; + break; + case fsl_e500mc: + /* e500mc */ + tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512); + tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); + env->dcache_line_size = 64; + env->icache_line_size = 64; break; default: cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]); @@ -4522,20 +4561,23 @@ static void init_proc_e500 (CPUPPCState *env, int version) #endif init_excp_e200(env); - env->dcache_line_size = 32; - env->icache_line_size = 32; /* Allocate hardware IRQ controller */ ppce500_irq_init(env); } static void init_proc_e500v1(CPUPPCState *env) { - init_proc_e500(env, 1); + init_proc_e500(env, fsl_e500v1); } static void init_proc_e500v2(CPUPPCState *env) { - init_proc_e500(env, 2); + init_proc_e500(env, fsl_e500v2); +} + +static void init_proc_e500mc(CPUPPCState *env) +{ + init_proc_e500(env, fsl_e500mc); } /* Non-embedded PowerPC */ @@ -7070,6 +7112,7 @@ enum { CPU_POWERPC_e500v2_v21 = 0x80210021, CPU_POWERPC_e500v2_v22 = 0x80210022, CPU_POWERPC_e500v2_v30 = 0x80210030, + CPU_POWERPC_e500mc = 0x80230020, /* MPC85xx microcontrollers */ #define CPU_POWERPC_MPC8533 CPU_POWERPC_MPC8533_v11 #define CPU_POWERPC_MPC8533_v10 CPU_POWERPC_e500v2_v21 @@ -8471,6 +8514,7 @@ static const ppc_def_t ppc_defs[] = { POWERPC_DEF("e500v2_v22", CPU_POWERPC_e500v2_v22, e500v2), /* PowerPC e500v2 v3.0 core */ POWERPC_DEF("e500v2_v30", CPU_POWERPC_e500v2_v30, e500v2), + POWERPC_DEF("e500mc", CPU_POWERPC_e500mc, e500mc), /* PowerPC e500 microcontrollers */ /* MPC8533 */ POWERPC_DEF_SVR("MPC8533",