@@ -64,6 +64,12 @@ PROPERTIES
device-trees omit this property on MPIC nodes even when the MPIC is
in fact big-endian, so certain boards override this property.
+ - single-cpu-affinity
+ Usage: optional
+ Value type: <empty>
+ If present the MPIC will be assumed to only be able to route
+ non-IPI interrupts to a single CPU at a time (EG: Freescale MPIC).
+
INTERRUPT SPECIFIER DEFINITION
Interrupt specifiers consists of 4 cells encoded as
@@ -40,6 +40,7 @@ mpic: pic@40000 {
compatible = "fsl,mpic";
device_type = "open-pic";
big-endian;
+ single-cpu-affinity;
};
timer@41100 {
@@ -1183,11 +1183,13 @@ struct mpic * __init mpic_alloc(struct device_node *node,
}
/* Read extra device-tree properties into the flags variable */
- if (of_get_property(mpic->node, "big-endian", NULL))
+ if (of_get_property(node, "big-endian", NULL))
flags |= MPIC_BIG_ENDIAN;
- if (of_get_property(mpic->node, "pic-no-reset", NULL))
+ if (of_get_property(node, "pic-no-reset", NULL))
flags |= MPIC_NO_RESET;
- if (of_device_is_compatible(mpic->node, "fsl,mpic"))
+ if (of_get_property(node, "single-cpu-affinity", NULL))
+ flags |= MPIC_SINGLE_DEST_CPU;
+ if (of_device_is_compatible(node, "fsl,mpic"))
flags |= MPIC_FSL;
mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
The Freescale MPIC (and perhaps others in the future) is incapable of routing non-IPI interrupts to more than once CPU at a time. Currently all of the Freescale boards msut pass the MPIC_SINGLE_DEST_CPU flag to mpic_alloc(), but that information should really be present in the device-tree. Older board code can't rely on the device-tree having the property set, but newer platforms won't need it manually specified in the code. Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> --- .../devicetree/bindings/powerpc/fsl/mpic.txt | 6 ++++++ arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi | 1 + arch/powerpc/sysdev/mpic.c | 8 +++++--- 3 files changed, 12 insertions(+), 3 deletions(-)