From patchwork Thu Dec 22 12:41:35 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen Jie-B02280 X-Patchwork-Id: 132840 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id D9277B716B for ; Thu, 22 Dec 2011 23:44:23 +1100 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1Rdhxw-00014R-Fl; Thu, 22 Dec 2011 12:41:44 +0000 Received: from db3ehsobe005.messaging.microsoft.com ([213.199.154.143] helo=DB3EHSOBE005.bigfish.com) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1Rdhxs-00014A-CU for linux-arm-kernel@lists.infradead.org; Thu, 22 Dec 2011 12:41:41 +0000 Received: from mail67-db3-R.bigfish.com (10.3.81.243) by DB3EHSOBE005.bigfish.com (10.3.84.25) with Microsoft SMTP Server id 14.1.225.23; Thu, 22 Dec 2011 12:41:27 +0000 Received: from mail67-db3 (localhost [127.0.0.1]) by mail67-db3-R.bigfish.com (Postfix) with ESMTP id 511081403F1; Thu, 22 Dec 2011 12:42:03 +0000 (UTC) X-SpamScore: 6 X-BigFish: VS6(z5109hzc89bhzz1202hzz8275dhz2dh2a8h668h839h8e2h8e3h941hbe9n) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail67-db3 (localhost.localdomain [127.0.0.1]) by mail67-db3 (MessageSwitch) id 1324557723166490_30442; Thu, 22 Dec 2011 12:42:03 +0000 (UTC) Received: from DB3EHSMHS017.bigfish.com (unknown [10.3.81.247]) by mail67-db3.bigfish.com (Postfix) with ESMTP id 22E1A500042; Thu, 22 Dec 2011 12:42:03 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by DB3EHSMHS017.bigfish.com (10.3.87.117) with Microsoft SMTP Server (TLS) id 14.1.225.23; Thu, 22 Dec 2011 12:41:26 +0000 Received: from 039-SN2MPN1-012.039d.mgd.msft.net ([169.254.2.253]) by 039-SN1MMR1-001.039d.mgd.msft.net ([10.84.1.13]) with mapi id 14.01.0355.003; Thu, 22 Dec 2011 06:41:36 -0600 From: Chen Jie-B02280 To: Jason Chen , "linux-arm-kernel@lists.infradead.org" Subject: =?gb2312?B?tPC4tDogW1BBVENIXSBhcm0vaW14NnE6IGFkZCBjbG9jayBkZWJ1Z2ZzIHN1?= =?gb2312?Q?pport?= Thread-Topic: [PATCH] arm/imx6q: add clock debugfs support Thread-Index: AQHMwKTYqHMHNTMD6kyWT0mZIN7mO5XnzIZ7 Date: Thu, 22 Dec 2011 12:41:35 +0000 Message-ID: <76DA9649941BC14A850EA090E8B0465E03A476@039-SN2MPN1-012.039d.mgd.msft.net> References: <1324556625-28192-1-git-send-email-jason.chen@linaro.org> In-Reply-To: <1324556625-28192-1-git-send-email-jason.chen@linaro.org> Accept-Language: zh-CN, en-US Content-Language: zh-CN X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.192.242.173] MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [213.199.154.143 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: "s.hauer@pengutronix.de" , "shawn.guo@linaro.org" , "eric.miao@linaro.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org sorry, pls ignore this mail which miss some commit, I will resend whole patch again. Jason Chen Tel: +86 21 28937178 Freescale Semiconductor (China) Limited Shanghai Branch Office No.192 Liangjing Rd., Pudong New Area, Shanghai, 201203 diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c index 9273c2a..840ab8d 100644 --- a/arch/arm/mach-imx/clock-imx6q.c +++ b/arch/arm/mach-imx/clock-imx6q.c @@ -335,6 +335,12 @@ #define FREQ_650M 650000000 #define FREQ_1300M 1300000000 +#ifdef CONFIG_CLK_DEBUG +#define __INIT_CLK_DEBUG(n) .name = #n, +#else +#define __INIT_CLK_DEBUG(n) +#endif + static struct clk pll1_sys; static struct clk pll2_bus; static struct clk pll3_usb_otg; @@ -415,14 +421,17 @@ static unsigned long get_low_reference_clock_rate(struct clk *clk) } static struct clk ckil_clk = { + __INIT_CLK_DEBUG(ckil_clk) .get_rate = get_low_reference_clock_rate, }; static struct clk ckih_clk = { + __INIT_CLK_DEBUG(ckih_clk) .get_rate = get_high_reference_clock_rate, }; static struct clk osc_clk = { + __INIT_CLK_DEBUG(osc_clk) .get_rate = get_oscillator_reference_clock_rate, }; @@ -677,6 +686,7 @@ static int pll_set_rate(struct clk *clk, unsigned long rate) #define DEF_PLL(name) \ static struct clk name = { \ + __INIT_CLK_DEBUG(name) \ .enable = pll_enable, \ .disable = pll_disable, \ .get_rate = name##_get_rate, \ @@ -796,6 +806,7 @@ static void pfd_disable(struct clk *clk) #define DEF_PFD(name, er, es, p) \ static struct clk name = { \ + __INIT_CLK_DEBUG(name) \ .enable_reg = er, \ .enable_shift = es, \ .enable = pfd_enable, \ @@ -820,6 +831,7 @@ static unsigned long pll2_200m_get_rate(struct clk *clk) } static struct clk pll2_200m = { + __INIT_CLK_DEBUG(pll2_200m) .parent = &pll2_pfd_400m, .get_rate = pll2_200m_get_rate, }; @@ -830,6 +842,7 @@ static unsigned long pll3_120m_get_rate(struct clk *clk) } static struct clk pll3_120m = { + __INIT_CLK_DEBUG(pll3_120m) .parent = &pll3_usb_otg, .get_rate = pll3_120m_get_rate, }; @@ -840,6 +853,7 @@ static unsigned long pll3_80m_get_rate(struct clk *clk) } static struct clk pll3_80m = { + __INIT_CLK_DEBUG(pll3_80m) .parent = &pll3_usb_otg, .get_rate = pll3_80m_get_rate, }; @@ -850,6 +864,7 @@ static unsigned long pll3_60m_get_rate(struct clk *clk) } static struct clk pll3_60m = { + __INIT_CLK_DEBUG(pll3_60m) .parent = &pll3_usb_otg, .get_rate = pll3_60m_get_rate, }; @@ -877,6 +892,7 @@ static int pll1_sw_clk_set_parent(struct clk *clk, struct clk *parent) } static struct clk pll1_sw_clk = { + __INIT_CLK_DEBUG(pll1_sw_clk) .parent = &pll1_sys, .set_parent = pll1_sw_clk_set_parent, }; @@ -1696,6 +1712,7 @@ static int _clk_set_parent(struct clk *clk, struct clk *parent) #define DEF_NG_CLK(name, p) \ static struct clk name = { \ + __INIT_CLK_DEBUG(name) \ .get_rate = _clk_get_rate, \ .set_rate = _clk_set_rate, \ .round_rate = _clk_round_rate, \ @@ -1723,6 +1740,7 @@ DEF_NG_CLK(asrc_serial_clk, &pll3_usb_otg); #define DEF_CLK(name, er, es, p, s) \ static struct clk name = { \ + __INIT_CLK_DEBUG(name) \ .enable_reg = er, \ .enable_shift = es, \ .enable = _clk_enable, \ @@ -1825,6 +1843,7 @@ static void pcie_clk_disable(struct clk *clk) } static struct clk pcie_clk = { + __INIT_CLK_DEBUG(pcie_clk) .enable_reg = CCGR4, .enable_shift = CG0, .enable = pcie_clk_enable, @@ -1857,6 +1876,7 @@ static void sata_clk_disable(struct clk *clk) } static struct clk sata_clk = { + __INIT_CLK_DEBUG(sata_clk) .enable_reg = CCGR5, .enable_shift = CG2, .enable = sata_clk_enable, @@ -1976,8 +1996,10 @@ int __init mx6q_clocks_init(void) oscillator_reference = rate; } - for (i = 0; i < ARRAY_SIZE(lookups); i++) + for (i = 0; i < ARRAY_SIZE(lookups); i++) { clkdev_add(&lookups[i]); + clk_debug_register(lookups[i].clk); + } /* only keep necessary clocks on */ writel_relaxed(0x3 << CG0 | 0x3 << CG1 | 0x3 << CG2, CCGR0);