[07/10] mips: Fix some insn types for Loongson.

Submitted by Richard Henderson on Dec. 21, 2011, 5 p.m.

Details

Message ID 1324486822-18225-8-git-send-email-rth@redhat.com
State New
Headers show

Commit Message

Richard Henderson Dec. 21, 2011, 5 p.m.
Tables 63 and 64 show the multimedia insn and the fpu insn on which
it is mapped.  The last bullet of 12.1 explicitly says that this is
meaningful for looking up the latency in Table 61.
---
 gcc/config/mips/loongson.md |   16 ++++++++--------
 1 files changed, 8 insertions(+), 8 deletions(-)

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diff --git a/gcc/config/mips/loongson.md b/gcc/config/mips/loongson.md
index c80a45a..8743984 100644
--- a/gcc/config/mips/loongson.md
+++ b/gcc/config/mips/loongson.md
@@ -143,7 +143,7 @@ 
 	  (match_operand:SI 2 "register_operand" "f")))]
   "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
   "punpcklwd\t%0,%1,%2"
-  [(set_attr "type" "fdiv")])
+  [(set_attr "type" "fcvt")])
 
 ;; Instruction patterns for SIMD instructions.
 
@@ -239,7 +239,7 @@ 
 		  (match_operand:VWHB 2 "register_operand" "f")))]
   "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
   "or\t%0,%1,%2"
-  [(set_attr "type" "fmul")])
+  [(set_attr "type" "fcvt")])
 
 ;; Logical XOR.
 (define_insn "xor<mode>3"
@@ -306,7 +306,7 @@ 
 		   UNSPEC_LOONGSON_PEXTR))]
   "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
   "pextrh\t%0,%1,%2"
-  [(set_attr "type" "fmul")])
+  [(set_attr "type" "fcvt")])
 
 ;; Insert halfword.
 (define_insn "loongson_pinsrh_0"
@@ -520,7 +520,7 @@ 
 		    (match_operand:SI 2 "register_operand" "f")))]
   "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
   "psll<V_suffix>\t%0,%1,%2"
-  [(set_attr "type" "fmul")])
+  [(set_attr "type" "fcvt")])
 
 ;; Shift right arithmetic.
 (define_insn "ashr<mode>3"
@@ -529,7 +529,7 @@ 
 		      (match_operand:SI 2 "register_operand" "f")))]
   "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
   "psra<V_suffix>\t%0,%1,%2"
-  [(set_attr "type" "fdiv")])
+  [(set_attr "type" "fcvt")])
 
 ;; Shift right logical.
 (define_insn "lshr<mode>3"
@@ -538,7 +538,7 @@ 
 		      (match_operand:SI 2 "register_operand" "f")))]
   "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
   "psrl<V_suffix>\t%0,%1,%2"
-  [(set_attr "type" "fdiv")])
+  [(set_attr "type" "fcvt")])
 
 ;; Subtraction, treating overflow by wraparound.
 (define_insn "sub<mode>3"
@@ -616,7 +616,7 @@ 
 	  (parallel [(const_int 1) (const_int 3)])))]
   "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
   "punpckhwd\t%0,%1,%2"
-  [(set_attr "type" "fdiv")])
+  [(set_attr "type" "fcvt")])
 
 ;; Unpack low data.
 (define_insn "loongson_punpcklbh"
@@ -654,7 +654,7 @@ 
 	  (parallel [(const_int 0) (const_int 2)])))]
   "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
   "punpcklwd\t%0,%1,%2"
-  [(set_attr "type" "fdiv")])
+  [(set_attr "type" "fcvt")])
 
 (define_expand "vec_perm_const<mode>"
   [(match_operand:VWHB 0 "register_operand" "")