From patchwork Mon Dec 19 06:16:32 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 132159 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id C3F07B6FF2 for ; Mon, 19 Dec 2011 17:16:58 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9C83D281F6; Mon, 19 Dec 2011 07:16:55 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id aEe9xhddnllF; Mon, 19 Dec 2011 07:16:55 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DCA6328228; Mon, 19 Dec 2011 07:16:53 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2A21D28228 for ; Mon, 19 Dec 2011 07:16:51 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id alNYGZgJ2CJQ for ; Mon, 19 Dec 2011 07:16:49 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-iy0-f172.google.com (mail-iy0-f172.google.com [209.85.210.172]) by theia.denx.de (Postfix) with ESMTPS id 1B27F281F6 for ; Mon, 19 Dec 2011 07:16:47 +0100 (CET) Received: by iaek3 with SMTP id k3so8094183iae.3 for ; Sun, 18 Dec 2011 22:16:46 -0800 (PST) Received: by 10.50.36.225 with SMTP id t1mr25135550igj.92.1324275405934; Sun, 18 Dec 2011 22:16:45 -0800 (PST) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id mb4sm30304774igc.1.2011.12.18.22.16.42 (version=SSLv3 cipher=OTHER); Sun, 18 Dec 2011 22:16:45 -0800 (PST) From: Chander Kashyap To: u-boot@lists.denx.de Date: Mon, 19 Dec 2011 11:46:32 +0530 Message-Id: <1324275392-29237-1-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.5.4 Cc: linaro-dev@lists.linaro.org, bjlee@samsung.com, patches@linaro.org, mk7.kang@samsung.com, samsung@lists.linaro.org Subject: [U-Boot] [PATCH] Origen: Select SCLKMPLL as FIMD0 parent clock X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: Chander Kashyap --- board/samsung/origen/lowlevel_init.S | 5 +++++ board/samsung/origen/origen_setup.h | 12 ++++++++++++ 2 files changed, 17 insertions(+), 0 deletions(-) diff --git a/board/samsung/origen/lowlevel_init.S b/board/samsung/origen/lowlevel_init.S index 0eebbfc..9283201 100644 --- a/board/samsung/origen/lowlevel_init.S +++ b/board/samsung/origen/lowlevel_init.S @@ -158,6 +158,11 @@ system_clock_init: ldr r2, =CLK_SRC_PERIL0_OFFSET str r1, [r0, r2] + /* FIMD0 */ + ldr r1, =CLK_SRC_LCD0_VAL + ldr r2, =CLK_SRC_LCD0_OFFSET + str r1, [r0, r2] + /* wait ?us */ mov r1, #0x10000 3: subs r1, r1, #1 diff --git a/board/samsung/origen/origen_setup.h b/board/samsung/origen/origen_setup.h index d949ad2..94cccca 100644 --- a/board/samsung/origen/origen_setup.h +++ b/board/samsung/origen/origen_setup.h @@ -56,6 +56,8 @@ #define CLK_SRC_PERIL0_OFFSET 0xC250 #define CLK_DIV_PERIL0_OFFSET 0xC550 +#define CLK_SRC_LCD0_OFFSET 0xC234 + #define APLL_LOCK_OFFSET 0x14000 #define MPLL_LOCK_OFFSET 0x14008 #define APLL_CON0_OFFSET 0x14100 @@ -351,6 +353,16 @@ | (UART1_RATIO << 4) \ | (UART0_RATIO << 0)) +/* CLK_SRC_LCD0 */ +#define FIMD_SEL_SCLKMPLL 6 +#define MDNIE0_SEL_XUSBXTI 1 +#define MDNIE_PWM0_SEL_XUSBXTI 1 +#define MIPI0_SEL_XUSBXTI 1 +#define CLK_SRC_LCD0_VAL ((MIPI0_SEL_XUSBXTI << 12) \ + | (MDNIE_PWM0_SEL_XUSBXTI << 8) \ + | (MDNIE0_SEL_XUSBXTI << 4) \ + | (FIMD_SEL_SCLKMPLL << 0)) + /* Required period to generate a stable clock output */ /* PLL_LOCK_TIME */ #define PLL_LOCKTIME 0x1C20