From patchwork Thu Dec 15 20:51:12 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: jordan.l.justen@intel.com X-Patchwork-Id: 131729 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id DC5901007D6 for ; Fri, 16 Dec 2011 07:51:42 +1100 (EST) Received: from localhost ([::1]:59658 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RbIHB-000362-Eo for incoming@patchwork.ozlabs.org; Thu, 15 Dec 2011 15:51:37 -0500 Received: from eggs.gnu.org ([140.186.70.92]:56073) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RbIH1-0002xY-Hn for qemu-devel@nongnu.org; Thu, 15 Dec 2011 15:51:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RbIGz-0008WT-T1 for qemu-devel@nongnu.org; Thu, 15 Dec 2011 15:51:27 -0500 Received: from mga01.intel.com ([192.55.52.88]:9617) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RbIGz-0008W4-C4 for qemu-devel@nongnu.org; Thu, 15 Dec 2011 15:51:25 -0500 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP; 15 Dec 2011 12:51:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.71,315,1320652800"; d="scan'208";a="96678182" Received: from unknown (HELO jljusten-laptop.amr.corp.intel.com) ([10.255.13.17]) by fmsmga001.fm.intel.com with ESMTP; 15 Dec 2011 12:51:19 -0800 From: Jordan Justen To: qemu-devel@nongnu.org Date: Thu, 15 Dec 2011 12:51:12 -0800 Message-Id: <1323982273-13623-3-git-send-email-jordan.l.justen@intel.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1323982273-13623-1-git-send-email-jordan.l.justen@intel.com> References: <1323982273-13623-1-git-send-email-jordan.l.justen@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.88 Cc: Jordan Justen Subject: [Qemu-devel] [PATCH v9 2/3] pflash: Support read-only mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org When read-only mode is enabled, no changes will be made to the flash image in memory, and no bdrv_write calls will be made. For pflash_cfi01 (Intel), if the flash is in read-only mode then the status register will signal block erase error or program error when these operations are attempted. For pflash_cfi02 (AMD), if the flash is in read-only mode then the pflash will silently ignore all write/erase commands. Signed-off-by: Jordan Justen --- blockdev.c | 3 +- hw/pflash_cfi01.c | 44 +++++++++++++++++++--------- hw/pflash_cfi02.c | 83 ++++++++++++++++++++++++++++------------------------ 3 files changed, 77 insertions(+), 53 deletions(-) diff --git a/blockdev.c b/blockdev.c index dbf0251..9096ae6 100644 --- a/blockdev.c +++ b/blockdev.c @@ -556,7 +556,8 @@ DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi) /* CDROM is fine for any interface, don't check. */ ro = 1; } else if (ro == 1) { - if (type != IF_SCSI && type != IF_VIRTIO && type != IF_FLOPPY && type != IF_NONE) { + if (type != IF_SCSI && type != IF_VIRTIO && type != IF_FLOPPY && + type != IF_NONE && type != IF_PFLASH) { error_report("readonly not supported by this bus type"); goto err; } diff --git a/hw/pflash_cfi01.c b/hw/pflash_cfi01.c index 69b8e3d..1e0a053 100644 --- a/hw/pflash_cfi01.c +++ b/hw/pflash_cfi01.c @@ -283,8 +283,12 @@ static void pflash_write(pflash_t *pfl, target_phys_addr_t offset, TARGET_FMT_plx "\n", __func__, offset, pfl->sector_len); - memset(p + offset, 0xff, pfl->sector_len); - pflash_update(pfl, offset, pfl->sector_len); + if (!pfl->ro) { + memset(p + offset, 0xff, pfl->sector_len); + pflash_update(pfl, offset, pfl->sector_len); + } else { + pfl->status |= 0x20; /* Block erase error */ + } pfl->status |= 0x80; /* Ready! */ break; case 0x50: /* Clear status bits */ @@ -323,8 +327,12 @@ static void pflash_write(pflash_t *pfl, target_phys_addr_t offset, case 0x10: /* Single Byte Program */ case 0x40: /* Single Byte Program */ DPRINTF("%s: Single Byte Program\n", __func__); - pflash_data_write(pfl, offset, value, width, be); - pflash_update(pfl, offset, width); + if (!pfl->ro) { + pflash_data_write(pfl, offset, value, width, be); + pflash_update(pfl, offset, width); + } else { + pfl->status |= 0x10; /* Programming error */ + } pfl->status |= 0x80; /* Ready! */ pfl->wcycle = 0; break; @@ -372,7 +380,11 @@ static void pflash_write(pflash_t *pfl, target_phys_addr_t offset, case 2: switch (pfl->cmd) { case 0xe8: /* Block write */ - pflash_data_write(pfl, offset, value, width, be); + if (!pfl->ro) { + pflash_data_write(pfl, offset, value, width, be); + } else { + pfl->status |= 0x10; /* Programming error */ + } pfl->status |= 0x80; @@ -382,8 +394,12 @@ static void pflash_write(pflash_t *pfl, target_phys_addr_t offset, DPRINTF("%s: block write finished\n", __func__); pfl->wcycle++; - /* Flush the entire write buffer onto backing storage. */ - pflash_update(pfl, offset & mask, pfl->writeblock_size); + if (!pfl->ro) { + /* Flush the entire write buffer onto backing storage. */ + pflash_update(pfl, offset & mask, pfl->writeblock_size); + } else { + pfl->status |= 0x10; /* Programming error */ + } } pfl->counter--; @@ -605,13 +621,13 @@ pflash_t *pflash_cfi01_register(target_phys_addr_t base, } bdrv_attach_dev_nofail(pfl->bs, pfl); } -#if 0 /* XXX: there should be a bit to set up read-only, - * the same way the hardware does (with WP pin). - */ - pfl->ro = 1; -#else - pfl->ro = 0; -#endif + + if (pfl->bs) { + pfl->ro = bdrv_is_read_only(pfl->bs); + } else { + pfl->ro = 0; + } + pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl); pfl->base = base; pfl->sector_len = sector_len; diff --git a/hw/pflash_cfi02.c b/hw/pflash_cfi02.c index e5a63da..9e91bdd 100644 --- a/hw/pflash_cfi02.c +++ b/hw/pflash_cfi02.c @@ -329,35 +329,37 @@ static void pflash_write (pflash_t *pfl, target_phys_addr_t offset, DPRINTF("%s: write data offset " TARGET_FMT_plx " %08x %d\n", __func__, offset, value, width); p = pfl->storage; - switch (width) { - case 1: - p[offset] &= value; - pflash_update(pfl, offset, 1); - break; - case 2: - if (be) { - p[offset] &= value >> 8; - p[offset + 1] &= value; - } else { + if (!pfl->ro) { + switch (width) { + case 1: p[offset] &= value; - p[offset + 1] &= value >> 8; + pflash_update(pfl, offset, 1); + break; + case 2: + if (be) { + p[offset] &= value >> 8; + p[offset + 1] &= value; + } else { + p[offset] &= value; + p[offset + 1] &= value >> 8; + } + pflash_update(pfl, offset, 2); + break; + case 4: + if (be) { + p[offset] &= value >> 24; + p[offset + 1] &= value >> 16; + p[offset + 2] &= value >> 8; + p[offset + 3] &= value; + } else { + p[offset] &= value; + p[offset + 1] &= value >> 8; + p[offset + 2] &= value >> 16; + p[offset + 3] &= value >> 24; + } + pflash_update(pfl, offset, 4); + break; } - pflash_update(pfl, offset, 2); - break; - case 4: - if (be) { - p[offset] &= value >> 24; - p[offset + 1] &= value >> 16; - p[offset + 2] &= value >> 8; - p[offset + 3] &= value; - } else { - p[offset] &= value; - p[offset + 1] &= value >> 8; - p[offset + 2] &= value >> 16; - p[offset + 3] &= value >> 24; - } - pflash_update(pfl, offset, 4); - break; } pfl->status = 0x00 | ~(value & 0x80); /* Let's pretend write is immediate */ @@ -403,9 +405,11 @@ static void pflash_write (pflash_t *pfl, target_phys_addr_t offset, } /* Chip erase */ DPRINTF("%s: start chip erase\n", __func__); - memset(pfl->storage, 0xFF, pfl->chip_len); + if (!pfl->ro) { + memset(pfl->storage, 0xFF, pfl->chip_len); + pflash_update(pfl, 0, pfl->chip_len); + } pfl->status = 0x00; - pflash_update(pfl, 0, pfl->chip_len); /* Let's wait 5 seconds before chip erase is done */ qemu_mod_timer(pfl->timer, qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() * 5)); @@ -416,8 +420,10 @@ static void pflash_write (pflash_t *pfl, target_phys_addr_t offset, offset &= ~(pfl->sector_len - 1); DPRINTF("%s: start sector erase at " TARGET_FMT_plx "\n", __func__, offset); - memset(p + offset, 0xFF, pfl->sector_len); - pflash_update(pfl, offset, pfl->sector_len); + if (!pfl->ro) { + memset(p + offset, 0xFF, pfl->sector_len); + pflash_update(pfl, offset, pfl->sector_len); + } pfl->status = 0x00; /* Let's wait 1/2 second before sector erase is done */ qemu_mod_timer(pfl->timer, @@ -643,16 +649,17 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, } bdrv_attach_dev_nofail(pfl->bs, pfl); } + pflash_setup_mappings(pfl); pfl->rom_mode = 1; memory_region_add_subregion(get_system_memory(), pfl->base, &pfl->mem); -#if 0 /* XXX: there should be a bit to set up read-only, - * the same way the hardware does (with WP pin). - */ - pfl->ro = 1; -#else - pfl->ro = 0; -#endif + + if (pfl->bs) { + pfl->ro = bdrv_is_read_only(pfl->bs); + } else { + pfl->ro = 0; + } + pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl); pfl->sector_len = sector_len; pfl->width = width;