From patchwork Thu Dec 15 15:53:53 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [v5, 4/5] highbank: Unconditionally require l2x0 L2 cache controller support From: Dave Martin X-Patchwork-Id: 131680 Message-Id: <1323964434-6764-5-git-send-email-dave.martin@linaro.org> To: linux-arm-kernel@lists.infradead.org Cc: patches@linaro.org, Anton Vorontsov , Barry Song , Catalin Marinas , Colin Cross , Haojian Zhuang , John Linn , Kukjin Kim , Linus Walleij , linux-omap@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-sh@vger.kernel.org, linux-tegra@vger.kernel.org, Magnus Damm , Paul Mundt , Pawel Moll , Rob Herring , Sascha Hauer , Shawn Guo , Tony Lindgren , Will Deacon Date: Thu, 15 Dec 2011 15:53:53 +0000 If running in the Normal World on a TrustZone-enabled SoC, Linux does not have complete control over the L2 cache controller configuration. The kernel cannot work reliably on such platforms without the l2x0 cache support code built in. This patch unconditionally enables l2x0 support for the Highbank SoC. Thanks to Rob Herring for this suggestion. [1] [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2011-November/074495.html Signed-off-by: Dave Martin Acked-by: Rob Herring --- arch/arm/Kconfig | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index eca82f9..1792146 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -340,12 +340,12 @@ config ARCH_HIGHBANK select ARM_AMBA select ARM_GIC select ARM_TIMER_SP804 + select CACHE_L2X0 select CLKDEV_LOOKUP select CPU_V7 select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU select HAVE_SMP - select MIGHT_HAVE_CACHE_L2X0 select USE_OF help Support for the Calxeda Highbank SoC based boards.