diff mbox

[U-Boot,1/4] powerpc/83xx/km: update SDRAM parameters for km8321 boards

Message ID 1323876105-6522-1-git-send-email-holger.brunck@keymile.com
State Accepted
Commit 513e396b4fda8fe06d3e336ba74d31c75ef757db
Delegated to: Kim Phillips
Headers show

Commit Message

Holger Brunck Dec. 14, 2011, 3:21 p.m. UTC 
From: Marco Schmid <marco.schmid@keymile.com>

Measurements during HW basic test showed, that the SDRAM timing
has to be optimized. This patch adapted these timings accordingly.

Signed-off-by: Marco Schmid <marco.schmid@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
cc: Kim Phillips <kim.phillips@freescale.com>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
---
 include/configs/km/km8321-common.h |   24 ++++++++++++++----------
 1 files changed, 14 insertions(+), 10 deletions(-)

Comments

Heiko Schocher Dec. 15, 2011, 6:27 a.m. UTC | #1 
Hello Holger,

Holger Brunck wrote:
> From: Marco Schmid <marco.schmid@keymile.com>
> 
> Measurements during HW basic test showed, that the SDRAM timing
> has to be optimized. This patch adapted these timings accordingly.
> 
> Signed-off-by: Marco Schmid <marco.schmid@keymile.com>
> Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
> cc: Kim Phillips <kim.phillips@freescale.com>
> cc: Valentin Longchamp <valentin.longchamp@keymile.com>
> ---
>  include/configs/km/km8321-common.h |   24 ++++++++++++++----------
>  1 files changed, 14 insertions(+), 10 deletions(-)

Acked-by: Heiko Schocher <hs@denx.de>

bye,
Heiko
Kim Phillips Jan. 10, 2012, 2:14 a.m. UTC | #2 
On Wed, 14 Dec 2011 16:21:42 +0100
Holger Brunck <holger.brunck@keymile.com> wrote:

> From: Marco Schmid <marco.schmid@keymile.com>
> 
> Measurements during HW basic test showed, that the SDRAM timing
> has to be optimized. This patch adapted these timings accordingly.
> 
> Signed-off-by: Marco Schmid <marco.schmid@keymile.com>
> Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
> cc: Kim Phillips <kim.phillips@freescale.com>
> cc: Valentin Longchamp <valentin.longchamp@keymile.com>
> ---

applied 1-4 out of 4 patches to mpc83xx.

Thanks,

Kim
diff mbox

Patch

diff --git a/include/configs/km/km8321-common.h b/include/configs/km/km8321-common.h
index 902ae26..580b72f 100644
--- a/include/configs/km/km8321-common.h
+++ b/include/configs/km/km8321-common.h
@@ -70,7 +70,8 @@ 
 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 					 SDRAM_CFG_32_BE | \
-					 SDRAM_CFG_SREN)
+					 SDRAM_CFG_SREN | \
+					 SDRAM_CFG_HSE)
 
 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
 #define CONFIG_SYS_DDR_CLK_CNTL		(DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
@@ -82,7 +83,7 @@ 
 					 CSCONFIG_ROW_BIT_13 | \
 					 CSCONFIG_COL_BIT_10)
 
-#define CONFIG_SYS_DDR_MODE	0x47860252
+#define CONFIG_SYS_DDR_MODE	0x47860242
 #define CONFIG_SYS_DDR_MODE2	0x8080c000
 
 #define CONFIG_SYS_DDR_TIMING_0	((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
@@ -94,20 +95,20 @@ 
 				 (0 << TIMING_CFG0_WRT_SHIFT) | \
 				 (0 << TIMING_CFG0_RWT_SHIFT))
 
-#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_50) | \
+#define CONFIG_SYS_DDR_TIMING_1	((TIMING_CFG1_CASLAT_40) | \
 				 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 				 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
-				 (2 << TIMING_CFG1_WRREC_SHIFT) | \
-				 (6 << TIMING_CFG1_REFREC_SHIFT) | \
-				 (2 << TIMING_CFG1_ACTTORW_SHIFT) | \
-				 (6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
-				 (2 << TIMING_CFG1_PRETOACT_SHIFT))
+				 (3 << TIMING_CFG1_WRREC_SHIFT) | \
+				 (7 << TIMING_CFG1_REFREC_SHIFT) | \
+				 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
+				 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
+				 (3 << TIMING_CFG1_PRETOACT_SHIFT))
 
 #define CONFIG_SYS_DDR_TIMING_2	((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 				 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 				 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 				 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
-				 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
+				 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 				 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 				 (5 << TIMING_CFG2_CPO_SHIFT))
 
@@ -122,7 +123,10 @@ 
 /*
  * Local Bus Configuration & Clock Setup
  */
-#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_EADC_1 | LCRR_CLKDIV_2)
+#define CONFIG_SYS_LCRR_DBYP	0x80000000
+#define CONFIG_SYS_LCRR_EADC	0x00010000
+#define CONFIG_SYS_LCRR_CLKDIV	0x00000002
+
 #define CONFIG_SYS_LBC_LBCR	0x00000000
 
 /*