[3/3] arm-linux: Add libitm support.

Message ID 4EE69F28.8050704@redhat.com
State New
Headers show

Commit Message

Richard Henderson Dec. 13, 2011, 12:41 a.m.
Four small patches relative to the last set.

(1) Big thinko in how to set the EQ condition from the strex results.

    And surprisingly that wrong condition PASSES a large portion of the
    testsuite, by running through the ll/sc loop twice, with the first
    time being truly successful and the second time producing the
    boolean output that we wanted.

    However, this mistake was visible via infinite looping in one libitm test.

(2) Use syscall as discussed w/ Joseph.  It's been too many weeks since
    that exchange, and I can't remember if I actually forgot to do it
    or simply failed to merge patch sets properly across N machines.
    Sorry about that, anyway.

(3) Ramana's feedback re cpu_relax.

(4) Ramama's feedback re sjlj.S, specifically: thumb2 and movt.

Built (w/o bootstrap) and then built and tested libitm w/ -march={armv7-a,armv5te} {,-mthumb}.
Full testsuite run started; hopefully done overnight.

Full tree at

  git://repo.or.cz/gcc/rth.git rth/atomic/arm

if there's any doubt about what's relative to what.

Better?  Ok?

From 291880c393066ca9cf73f989521116c82f748b2c Mon Sep 17 00:00:00 2001
From: Richard Henderson <rth@redhat.com>
Date: Mon, 12 Dec 2011 18:22:21 -0500
Subject: [PATCH 1/4] fixup arm: end test for ll/sc

 gcc/config/arm/arm.c  |    8 ++++----
 gcc/config/arm/arm.md |   15 +--------------
 2 files changed, 5 insertions(+), 18 deletions(-)


diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 0b31ebb..f829a83 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -24755,13 +24755,13 @@  arm_split_compare_and_swap (rtx operands[])
   arm_emit_store_exclusive (mode, scratch, mem, newval);
   /* Weak or strong, we want EQ to be true for success, so that we
-     match the flags that we got from the compare above.  Thus we
-     prefer to use TEQ instead of TST here.  */
-  emit_insn (gen_xorsi3_compare0_scratch (scratch, const1_rtx));
+     match the flags that we got from the compare above.  */
+  cond = gen_rtx_REG (CCmode, CC_REGNUM);
+  x = gen_rtx_COMPARE (CCmode, scratch, const0_rtx);
+  emit_insn (gen_rtx_SET (VOIDmode, cond, x));
   if (!is_weak)
-      cond = gen_rtx_REG (CCmode, CC_REGNUM);
       x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
       x = gen_rtx_IF_THEN_ELSE (VOIDmode, x,
 				gen_rtx_LABEL_REF (Pmode, label1), pc_rtx);
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 2faf0ef..1af825d 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -3079,20 +3079,7 @@ 
   [(set_attr "conds" "set")]
-(define_insn "*xorsi3_compare0_scratch_arm"
-  [(set (reg:CC_NOOV CC_REGNUM)
-	(compare:CC_NOOV (xor:SI (match_operand:SI 0 "s_register_operand" "r")
-				 (match_operand:SI 1 "arm_rhs_operand" "rI"))
-			 (const_int 0)))]
-  "teq%?\\t%0, %1"
-  [(set_attr "conds" "set")
-   ; Not predicable via IT block (since it doesn't modify the flags there),
-   ; but we're keen on having this predicate in ARM mode for compare-and-swap.
-   (set_attr "predicable" "yes")]
-(define_insn "xorsi3_compare0_scratch"
+(define_insn "*xorsi3_compare0_scratch"
   [(set (reg:CC_NOOV CC_REGNUM)
 	(compare:CC_NOOV (xor:SI (match_operand:SI 0 "s_register_operand" "r")
 				 (match_operand:SI 1 "arm_rhs_operand" "rI"))