Patchwork [1/6] target-i386: Fix sloppy uses of i32/i64 functions

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Submitter Andreas Färber
Date Dec. 10, 2011, 12:58 p.m.
Message ID <1323521895-26693-2-git-send-email-andreas.faerber@web.de>
Download mbox | patch
Permalink /patch/130524/
State New
Headers show

Comments

Andreas Färber - Dec. 10, 2011, 12:58 p.m.
Use TCGv (tl) versions instead.

Signed-off-by: Andreas Färber <andreas.faerber@web.de>
---
 target-i386/translate.c |  130 +++++++++++++++++++++++-----------------------
 1 files changed, 65 insertions(+), 65 deletions(-)

Patch

diff --git a/target-i386/translate.c b/target-i386/translate.c
index 1ef8d16..0ffc450 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -3351,8 +3351,8 @@  static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         case 0x7e: /* movd ea, mm */
 #ifdef TARGET_X86_64
             if (s->dflag == 2) {
-                tcg_gen_ld_i64(cpu_T[0], cpu_env, 
-                               offsetof(CPUX86State,fpregs[reg].mmx));
+                tcg_gen_ld_tl(cpu_T[0], cpu_env, 
+                              offsetof(CPUX86State,fpregs[reg].mmx));
                 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
             } else
 #endif
@@ -3365,8 +3365,8 @@  static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         case 0x17e: /* movd ea, xmm */
 #ifdef TARGET_X86_64
             if (s->dflag == 2) {
-                tcg_gen_ld_i64(cpu_T[0], cpu_env, 
-                               offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
+                tcg_gen_ld_tl(cpu_T[0], cpu_env, 
+                              offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
                 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
             } else
 #endif
@@ -4427,14 +4427,14 @@  static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
                     t0 = tcg_temp_new_i64();
                     t1 = tcg_temp_new_i64();
                     gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
-                    tcg_gen_extu_i32_i64(t0, cpu_T[0]);
-                    tcg_gen_extu_i32_i64(t1, cpu_T[1]);
+                    tcg_gen_extu_tl_i64(t0, cpu_T[0]);
+                    tcg_gen_extu_tl_i64(t1, cpu_T[1]);
                     tcg_gen_mul_i64(t0, t0, t1);
-                    tcg_gen_trunc_i64_i32(cpu_T[0], t0);
+                    tcg_gen_trunc_i64_tl(cpu_T[0], t0);
                     gen_op_mov_reg_T0(OT_LONG, R_EAX);
                     tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
                     tcg_gen_shri_i64(t0, t0, 32);
-                    tcg_gen_trunc_i64_i32(cpu_T[0], t0);
+                    tcg_gen_trunc_i64_tl(cpu_T[0], t0);
                     gen_op_mov_reg_T0(OT_LONG, R_EDX);
                     tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
                 }
@@ -4496,15 +4496,15 @@  static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
                     t0 = tcg_temp_new_i64();
                     t1 = tcg_temp_new_i64();
                     gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
-                    tcg_gen_ext_i32_i64(t0, cpu_T[0]);
-                    tcg_gen_ext_i32_i64(t1, cpu_T[1]);
+                    tcg_gen_ext_tl_i64(t0, cpu_T[0]);
+                    tcg_gen_ext_tl_i64(t1, cpu_T[1]);
                     tcg_gen_mul_i64(t0, t0, t1);
-                    tcg_gen_trunc_i64_i32(cpu_T[0], t0);
+                    tcg_gen_trunc_i64_tl(cpu_T[0], t0);
                     gen_op_mov_reg_T0(OT_LONG, R_EAX);
                     tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
                     tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
                     tcg_gen_shri_i64(t0, t0, 32);
-                    tcg_gen_trunc_i64_i32(cpu_T[0], t0);
+                    tcg_gen_trunc_i64_tl(cpu_T[0], t0);
                     gen_op_mov_reg_T0(OT_LONG, R_EDX);
                     tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
                 }
@@ -4789,14 +4789,14 @@  static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
                     TCGv_i64 t0, t1;
                     t0 = tcg_temp_new_i64();
                     t1 = tcg_temp_new_i64();
-                    tcg_gen_ext_i32_i64(t0, cpu_T[0]);
-                    tcg_gen_ext_i32_i64(t1, cpu_T[1]);
+                    tcg_gen_ext_tl_i64(t0, cpu_T[0]);
+                    tcg_gen_ext_tl_i64(t1, cpu_T[1]);
                     tcg_gen_mul_i64(t0, t0, t1);
-                    tcg_gen_trunc_i64_i32(cpu_T[0], t0);
+                    tcg_gen_trunc_i64_tl(cpu_T[0], t0);
                     tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
                     tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
                     tcg_gen_shri_i64(t0, t0, 32);
-                    tcg_gen_trunc_i64_i32(cpu_T[1], t0);
+                    tcg_gen_trunc_i64_tl(cpu_T[1], t0);
                     tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0);
                 }
 #endif
@@ -6772,7 +6772,7 @@  static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
 #ifdef TARGET_X86_64
         if (dflag == 2) {
             gen_op_mov_TN_reg(OT_QUAD, 0, reg);
-            tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
+            tcg_gen_bswap64_tl(cpu_T[0], cpu_T[0]);
             gen_op_mov_reg_T0(OT_QUAD, reg);
         } else
 #endif
@@ -7650,55 +7650,55 @@  void optimize_flags_init(void)
                                     "cc_tmp");
 
 #ifdef TARGET_X86_64
-    cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_EAX]), "rax");
-    cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_ECX]), "rcx");
-    cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_EDX]), "rdx");
-    cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_EBX]), "rbx");
-    cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_ESP]), "rsp");
-    cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_EBP]), "rbp");
-    cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_ESI]), "rsi");
-    cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_EDI]), "rdi");
-    cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0,
-                                         offsetof(CPUState, regs[8]), "r8");
-    cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0,
-                                          offsetof(CPUState, regs[9]), "r9");
-    cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0,
-                                          offsetof(CPUState, regs[10]), "r10");
-    cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0,
-                                          offsetof(CPUState, regs[11]), "r11");
-    cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0,
-                                          offsetof(CPUState, regs[12]), "r12");
-    cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0,
-                                          offsetof(CPUState, regs[13]), "r13");
-    cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0,
-                                          offsetof(CPUState, regs[14]), "r14");
-    cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0,
-                                          offsetof(CPUState, regs[15]), "r15");
+    cpu_regs[R_EAX] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_EAX]), "rax");
+    cpu_regs[R_ECX] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_ECX]), "rcx");
+    cpu_regs[R_EDX] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_EDX]), "rdx");
+    cpu_regs[R_EBX] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_EBX]), "rbx");
+    cpu_regs[R_ESP] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_ESP]), "rsp");
+    cpu_regs[R_EBP] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_EBP]), "rbp");
+    cpu_regs[R_ESI] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_ESI]), "rsi");
+    cpu_regs[R_EDI] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_EDI]), "rdi");
+    cpu_regs[8] = tcg_global_mem_new(TCG_AREG0,
+                                     offsetof(CPUState, regs[8]), "r8");
+    cpu_regs[9] = tcg_global_mem_new(TCG_AREG0,
+                                     offsetof(CPUState, regs[9]), "r9");
+    cpu_regs[10] = tcg_global_mem_new(TCG_AREG0,
+                                      offsetof(CPUState, regs[10]), "r10");
+    cpu_regs[11] = tcg_global_mem_new(TCG_AREG0,
+                                      offsetof(CPUState, regs[11]), "r11");
+    cpu_regs[12] = tcg_global_mem_new(TCG_AREG0,
+                                      offsetof(CPUState, regs[12]), "r12");
+    cpu_regs[13] = tcg_global_mem_new(TCG_AREG0,
+                                      offsetof(CPUState, regs[13]), "r13");
+    cpu_regs[14] = tcg_global_mem_new(TCG_AREG0,
+                                      offsetof(CPUState, regs[14]), "r14");
+    cpu_regs[15] = tcg_global_mem_new(TCG_AREG0,
+                                      offsetof(CPUState, regs[15]), "r15");
 #else
-    cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_EAX]), "eax");
-    cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_ECX]), "ecx");
-    cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_EDX]), "edx");
-    cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_EBX]), "ebx");
-    cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_ESP]), "esp");
-    cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_EBP]), "ebp");
-    cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_ESI]), "esi");
-    cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0,
-                                             offsetof(CPUState, regs[R_EDI]), "edi");
+    cpu_regs[R_EAX] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_EAX]), "eax");
+    cpu_regs[R_ECX] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_ECX]), "ecx");
+    cpu_regs[R_EDX] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_EDX]), "edx");
+    cpu_regs[R_EBX] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_EBX]), "ebx");
+    cpu_regs[R_ESP] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_ESP]), "esp");
+    cpu_regs[R_EBP] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_EBP]), "ebp");
+    cpu_regs[R_ESI] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_ESI]), "esi");
+    cpu_regs[R_EDI] = tcg_global_mem_new(TCG_AREG0,
+                                         offsetof(CPUState, regs[R_EDI]), "edi");
 #endif
 
     /* register helpers */