From patchwork Tue Dec 6 12:58:14 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Kiszka X-Patchwork-Id: 129687 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 297D6B6F9B for ; Wed, 7 Dec 2011 00:52:15 +1100 (EST) Received: from localhost ([::1]:54363 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RXucZ-0003GS-Dc for incoming@patchwork.ozlabs.org; Tue, 06 Dec 2011 07:59:43 -0500 Received: from eggs.gnu.org ([140.186.70.92]:59010) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RXubc-000107-Pt for qemu-devel@nongnu.org; Tue, 06 Dec 2011 07:58:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RXubU-0002dF-Nf for qemu-devel@nongnu.org; Tue, 06 Dec 2011 07:58:44 -0500 Received: from goliath.siemens.de ([192.35.17.28]:21846) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RXubU-0002d4-8G for qemu-devel@nongnu.org; Tue, 06 Dec 2011 07:58:36 -0500 Received: from mail1.siemens.de (localhost [127.0.0.1]) by goliath.siemens.de (8.13.6/8.13.6) with ESMTP id pB6CwXAI014337; Tue, 6 Dec 2011 13:58:33 +0100 Received: from mchn199C.mchp.siemens.de ([139.25.109.49]) by mail1.siemens.de (8.13.6/8.13.6) with ESMTP id pB6CwHqH011829; Tue, 6 Dec 2011 13:58:33 +0100 From: Jan Kiszka To: Avi Kivity , Marcelo Tosatti Date: Tue, 6 Dec 2011 13:58:14 +0100 Message-Id: <0cea37dbe26721404a996418de4fd88c2b6eb13f.1323176291.git.jan.kiszka@siemens.com> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) X-Received-From: 192.35.17.28 Cc: Blue Swirl , Anthony Liguori , qemu-devel , kvm@vger.kernel.org, "Michael S. Tsirkin" Subject: [Qemu-devel] [PATCH v3 14/16] kvm: x86: Add user space part for in-kernel i8259 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Introduce the alternative i8259 backend that exploits KVM in-kernel acceleration. The PIIX3 initialization code is furthermore extended by KVM specific IRQ route setup. GSI injection differs in KVM mode from the user space model. As we can dispatch ISA-range IRQs to both IOAPIC and PIC inside the kernel, we do not need to inject them separately. This is reflected by a KVM-specific GSI handler. Signed-off-by: Jan Kiszka --- Makefile.target | 2 +- hw/kvm/i8259.c | 126 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ hw/pc.h | 1 + hw/pc_piix.c | 50 ++++++++++++++++++++-- 4 files changed, 174 insertions(+), 5 deletions(-) create mode 100644 hw/kvm/i8259.c diff --git a/Makefile.target b/Makefile.target index 66b42d5..850b80f 100644 --- a/Makefile.target +++ b/Makefile.target @@ -231,7 +231,7 @@ obj-i386-y += vmport.o obj-i386-y += device-hotplug.o pci-hotplug.o smbios.o wdt_ib700.o obj-i386-y += debugcon.o multiboot.o obj-i386-y += pc_piix.o -obj-i386-$(CONFIG_KVM) += kvm/clock.o kvm/apic.o +obj-i386-$(CONFIG_KVM) += kvm/clock.o kvm/apic.o kvm/i8259.o obj-i386-$(CONFIG_SPICE) += qxl.o qxl-logger.o qxl-render.o # shared objects diff --git a/hw/kvm/i8259.c b/hw/kvm/i8259.c new file mode 100644 index 0000000..98d7141 --- /dev/null +++ b/hw/kvm/i8259.c @@ -0,0 +1,126 @@ +/* + * KVM in-kernel PIC (i8259) support + * + * Copyright (c) 2011 Siemens AG + * + * Authors: + * Jan Kiszka + * + * This work is licensed under the terms of the GNU GPL version 2. + * See the COPYING file in the top-level directory. + */ +#include "hw/i8259_internal.h" +#include "hw/apic_internal.h" +#include "kvm.h" + +static void kvm_pic_get(PicState *s) +{ + struct kvm_irqchip chip; + struct kvm_pic_state *kpic; + int ret; + + chip.chip_id = s->master ? KVM_IRQCHIP_PIC_MASTER : KVM_IRQCHIP_PIC_SLAVE; + ret = kvm_vm_ioctl(kvm_state, KVM_GET_IRQCHIP, &chip); + if (ret < 0) { + fprintf(stderr, "KVM_GET_IRQCHIP failed: %s\n", strerror(ret)); + abort(); + } + + kpic = &chip.chip.pic; + + s->last_irr = kpic->last_irr; + s->irr = kpic->irr; + s->imr = kpic->imr; + s->isr = kpic->isr; + s->priority_add = kpic->priority_add; + s->irq_base = kpic->irq_base; + s->read_reg_select = kpic->read_reg_select; + s->poll = kpic->poll; + s->special_mask = kpic->special_mask; + s->init_state = kpic->init_state; + s->auto_eoi = kpic->auto_eoi; + s->rotate_on_auto_eoi = kpic->rotate_on_auto_eoi; + s->special_fully_nested_mode = kpic->special_fully_nested_mode; + s->init4 = kpic->init4; + s->elcr = kpic->elcr; + s->elcr_mask = kpic->elcr_mask; +} + +static void kvm_pic_put(PicState *s) +{ + struct kvm_irqchip chip; + struct kvm_pic_state *kpic; + int ret; + + chip.chip_id = s->master ? KVM_IRQCHIP_PIC_MASTER : KVM_IRQCHIP_PIC_SLAVE; + + kpic = &chip.chip.pic; + + kpic->last_irr = s->last_irr; + kpic->irr = s->irr; + kpic->imr = s->imr; + kpic->isr = s->isr; + kpic->priority_add = s->priority_add; + kpic->irq_base = s->irq_base; + kpic->read_reg_select = s->read_reg_select; + kpic->poll = s->poll; + kpic->special_mask = s->special_mask; + kpic->init_state = s->init_state; + kpic->auto_eoi = s->auto_eoi; + kpic->rotate_on_auto_eoi = s->rotate_on_auto_eoi; + kpic->special_fully_nested_mode = s->special_fully_nested_mode; + kpic->init4 = s->init4; + kpic->elcr = s->elcr; + kpic->elcr_mask = s->elcr_mask; + + ret = kvm_vm_ioctl(kvm_state, KVM_SET_IRQCHIP, &chip); + if (ret < 0) { + fprintf(stderr, "KVM_GET_IRQCHIP failed: %s\n", strerror(ret)); + abort(); + } +} + +static void kvm_pic_reset(PicState *s) +{ + pic_reset_internal(s); + s->elcr = 0; + + kvm_pic_put(s); +} + +static void kvm_pic_set_irq(void *opaque, int irq, int level) +{ + int delivered; + + delivered = kvm_irqchip_set_irq(kvm_state, irq, level); + apic_set_irq_delivered(delivered); +} + +static void kvm_pic_backend_init(PicState *s) +{ + memory_region_init_reservation(&s->base_io, "kvm-pic", 2); + memory_region_init_reservation(&s->elcr_io, "kvm-elcr", 1); +} + +qemu_irq *kvm_i8259_init(void) +{ + i8259_init_chip(true, "KVM"); + i8259_init_chip(false, "KVM"); + + return qemu_allocate_irqs(kvm_pic_set_irq, NULL, ISA_NUM_IRQS); +} + +static PICBackend kvm_pic_backend = { + .name = "KVM", + .init = kvm_pic_backend_init, + .reset = kvm_pic_reset, + .pre_save = kvm_pic_get, + .post_load = kvm_pic_put, +}; + +static void kvm_pic_register(void) +{ + pic_register_backend(&kvm_pic_backend); +} + +device_init(kvm_pic_register) diff --git a/hw/pc.h b/hw/pc.h index b8ad9a3..d8e7313 100644 --- a/hw/pc.h +++ b/hw/pc.h @@ -63,6 +63,7 @@ bool parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, typedef struct PicState PicState; extern PicState *isa_pic; qemu_irq *i8259_init(qemu_irq parent_irq); +qemu_irq *kvm_i8259_init(void); int pic_read_irq(PicState *s); int pic_get_output(PicState *s); void pic_info(Monitor *mon); diff --git a/hw/pc_piix.c b/hw/pc_piix.c index 22997b0..351b032 100644 --- a/hw/pc_piix.c +++ b/hw/pc_piix.c @@ -53,6 +53,40 @@ static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 }; static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 }; static const int ide_irq[MAX_IDE_BUS] = { 14, 15 }; +static void kvm_piix3_setup_irq_routing(bool pci_enabled) +{ + KVMState *s = kvm_state; + int ret, i; + + if (kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) { + for (i = 0; i < 8; ++i) { + if (i == 2) { + continue; + } + kvm_irqchip_add_route(s, i, KVM_IRQCHIP_PIC_MASTER, i); + } + for (i = 8; i < 16; ++i) { + kvm_irqchip_add_route(s, i, KVM_IRQCHIP_PIC_SLAVE, i - 8); + } + ret = kvm_irqchip_commit_routes(s); + if (ret < 0) { + hw_error("KVM IRQ routing setup failed"); + } + } +} + +static void kvm_piix3_gsi_handler(void *opaque, int n, int level) +{ + GSIState *s = opaque; + + if (n < ISA_NUM_IRQS) { + /* Kernel will forward to both PIC and IOAPIC */ + qemu_set_irq(s->i8259_irq[n], level); + } else { + qemu_set_irq(s->ioapic_irq[n], level); + } +} + static void ioapic_init(GSIState *gsi_state) { DeviceState *dev; @@ -131,7 +165,13 @@ static void pc_init1(MemoryRegion *system_memory, } gsi_state = g_malloc0(sizeof(*gsi_state)); - gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); + if (kvm_enabled() && kvm_irqchip_in_kernel()) { + kvm_piix3_setup_irq_routing(pci_enabled); + gsi = qemu_allocate_irqs(kvm_piix3_gsi_handler, gsi_state, + GSI_NUM_PINS); + } else { + gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS); + } if (pci_enabled) { pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, gsi, @@ -151,11 +191,13 @@ static void pc_init1(MemoryRegion *system_memory, } isa_bus_irqs(gsi); - if (!xen_enabled()) { + if (kvm_enabled() && kvm_irqchip_in_kernel()) { + i8259 = kvm_i8259_init(); + } else if (xen_enabled()) { + i8259 = xen_interrupt_controller_init(); + } else { cpu_irq = pc_allocate_cpu_irq(); i8259 = i8259_init(cpu_irq[0]); - } else { - i8259 = xen_interrupt_controller_init(); } for (i = 0; i < ISA_NUM_IRQS; i++) {