diff --git a/board/chromebook-x86/coreboot/coreboot_pci.c b/board/chromebook-x86/coreboot/coreboot_pci.c
index 732ca3c..2ec6059 100644
--- a/board/chromebook-x86/coreboot/coreboot_pci.c
+++ b/board/chromebook-x86/coreboot/coreboot_pci.c
@@ -25,6 +25,39 @@
  * MA 02111-1307 USA
  */
 
+#include <common.h>
+#include <pci.h>
+#include <asm/pci.h>
+
+static struct pci_controller coreboot_hose;
+
+#define X86_PCI_CONFIG_ADDR 0xCF8
+#define X86_PCI_CONFIG_DATA 0xCFC
+
+static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
+			      struct pci_config_table *table)
+{
+	u8 secondary;
+	hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
+	hose->last_busno = max(hose->last_busno, secondary);
+	pci_hose_scan_bus(hose, secondary);
+}
+
+static struct pci_config_table pci_coreboot_config_table[] = {
+	/* vendor, device, class, bus, dev, func */
+	{ PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
+	  PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge},
+	{}
+};
+
 void pci_init_board(void)
 {
+	coreboot_hose.config_table = pci_coreboot_config_table;
+	coreboot_hose.first_busno = 0;
+	coreboot_hose.last_busno = 0;
+	coreboot_hose.region_count = 0;
+
+	pci_setup_type1(&coreboot_hose);
+	pci_register_hose(&coreboot_hose);
+	pci_hose_scan(&coreboot_hose);
 }