Patchwork [U-Boot] i.mx: i.mx6q: add the initial support for i.mx6q Sabre Lite board

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Submitter Jason Liu
Date Dec. 5, 2011, 12:57 p.m.
Message ID <1323089828-20841-1-git-send-email-jason.hui@linaro.org>
Download mbox | patch
Permalink /patch/129285/
State Changes Requested
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Comments

Jason Liu - Dec. 5, 2011, 12:57 p.m.
From: Dirk Behme <dirk.behme@de.bosch.com>

Add the initial support for Freescale i.MX6Q Sabre Lite board

Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: Jason Liu <jason.hui@linaro.org>
Cc: Stefano Babic <sbabic@denx.de>
---
 MAINTAINERS                                   |    1 +
 board/freescale/mx6qsabrelite/Makefile        |   42 ++++++
 board/freescale/mx6qsabrelite/imximage.cfg    |  170 +++++++++++++++++++++++++
 board/freescale/mx6qsabrelite/mx6qsabrelite.c |  150 ++++++++++++++++++++++
 boards.cfg                                    |    1 +
 include/configs/mx6qsabrelite.h               |  158 +++++++++++++++++++++++
 6 files changed, 522 insertions(+), 0 deletions(-)
Fabio Estevam - Dec. 5, 2011, 1:23 p.m.
On Mon, Dec 5, 2011 at 10:57 AM, Jason Liu <jason.hui@linaro.org> wrote:

> +IMAGE_VERSION 2
> +
> +# Boot Device : one of
> +# spi, sd (the board has no nand neither onenand)
> +
> +BOOT_FROM      sd

This board does not boot from sd, only from SPI NOR.

Could you please let me know how it was tested?

It would be nice to add a README that tells how to flash the SPI NOR.

Regards,

Fabio Estevam
Dirk Behme - Dec. 5, 2011, 1:26 p.m.
On 05.12.2011 14:23, Fabio Estevam wrote:
> On Mon, Dec 5, 2011 at 10:57 AM, Jason Liu <jason.hui@linaro.org> wrote:
> 
>> +IMAGE_VERSION 2
>> +
>> +# Boot Device : one of
>> +# spi, sd (the board has no nand neither onenand)
>> +
>> +BOOT_FROM      sd
> 
> This board does not boot from sd, only from SPI NOR.
> 
> Could you please let me know how it was tested?

There is a 'workaround/patch' available from Freescale which switches 
the board to SD boot. It's a small program written to the SPI NOR 
replacing the U-Boot in SPI NOR, which then itself jumps back to the SD 
boot routines. From user point of view the boards boots from SD then. 
With a small, invisible indirection via the SPI NOR.

Best regards

Dirk
Dirk Behme - Dec. 5, 2011, 1:32 p.m.
On 05.12.2011 13:57, Jason Liu wrote:
> From: Dirk Behme <dirk.behme@de.bosch.com>
> 
> Add the initial support for Freescale i.MX6Q Sabre Lite board

Please note that this patch relies on the basic i.mx6q core support 
introduced with the patch series

http://lists.denx.de/pipermail/u-boot/2011-November/111163.html

So it would be nice if this patch could be handled together with the 
above patch series as proposed in

http://lists.denx.de/pipermail/u-boot/2011-December/111881.html

Many thanks

Dirk
Fabio Estevam - Dec. 5, 2011, 2:09 p.m.
On Mon, Dec 5, 2011 at 11:26 AM, Dirk Behme <dirk.behme@de.bosch.com> wrote:
> On 05.12.2011 14:23, Fabio Estevam wrote:
>>
>> On Mon, Dec 5, 2011 at 10:57 AM, Jason Liu <jason.hui@linaro.org> wrote:
>>
>>> +IMAGE_VERSION 2
>>> +
>>> +# Boot Device : one of
>>> +# spi, sd (the board has no nand neither onenand)
>>> +
>>> +BOOT_FROM      sd
>>
>>
>> This board does not boot from sd, only from SPI NOR.
>>
>> Could you please let me know how it was tested?
>
>
> There is a 'workaround/patch' available from Freescale which switches the
> board to SD boot. It's a small program written to the SPI NOR replacing the
> U-Boot in SPI NOR, which then itself jumps back to the SD boot routines.
> From user point of view the boards boots from SD then. With a small,
> invisible indirection via the SPI NOR.

I would be glad to test the mx6sabrelite U-boot patch if you can provide me the
FSL workaround/patch that replaces SPI NOR with SD boot.

Thanks,

Fabio Estevam
Stefano Babic - Dec. 6, 2011, 8:46 a.m.
On 05/12/2011 14:26, Dirk Behme wrote:
> On 05.12.2011 14:23, Fabio Estevam wrote:
>> On Mon, Dec 5, 2011 at 10:57 AM, Jason Liu <jason.hui@linaro.org> wrote:
>>
>>> +IMAGE_VERSION 2
>>> +
>>> +# Boot Device : one of
>>> +# spi, sd (the board has no nand neither onenand)
>>> +
>>> +BOOT_FROM      sd
>>
>> This board does not boot from sd, only from SPI NOR.
>>
>> Could you please let me know how it was tested?
> 

Hi Dirk,

> There is a 'workaround/patch' available from Freescale which switches
> the board to SD boot. It's a small program written to the SPI NOR
> replacing the U-Boot in SPI NOR, which then itself jumps back to the SD
> boot routines. From user point of view the boards boots from SD then.

But if I really understand, the board boots always from SPI NOR, in
other words the SPI NOR cannot be empty, as it can be if the board boots
drirectly from SD.

> With a small, invisible indirection via the SPI NOR.

Then we need a document / README, as remarked by Fabio, to describe this
process.

Best regards,
Stefano Babic
Dirk Behme - Dec. 6, 2011, 9:41 a.m.
On 06.12.2011 09:46, Stefano Babic wrote:
> On 05/12/2011 14:26, Dirk Behme wrote:
>> On 05.12.2011 14:23, Fabio Estevam wrote:
>>> On Mon, Dec 5, 2011 at 10:57 AM, Jason Liu <jason.hui@linaro.org> wrote:
>>>
>>>> +IMAGE_VERSION 2
>>>> +
>>>> +# Boot Device : one of
>>>> +# spi, sd (the board has no nand neither onenand)
>>>> +
>>>> +BOOT_FROM      sd
>>> This board does not boot from sd, only from SPI NOR.
>>>
>>> Could you please let me know how it was tested?
> 
> Hi Dirk,
> 
>> There is a 'workaround/patch' available from Freescale which switches
>> the board to SD boot. It's a small program written to the SPI NOR
>> replacing the U-Boot in SPI NOR, which then itself jumps back to the SD
>> boot routines. From user point of view the boards boots from SD then.
> 
> But if I really understand, the board boots always from SPI NOR, in
> other words the SPI NOR cannot be empty, as it can be if the board boots
> drirectly from SD.

Yes, this is correct. The ~20 line workaround is executed first in the 
SPI NOR and then jumps back to the SD boot routines. Hopefully there 
will be updated/modified boards in the future were the boot mode is 
configurable, again.

>> With a small, invisible indirection via the SPI NOR.
> 
> Then we need a document / README, as remarked by Fabio, to describe this
> process.

Fabio: Do you think you could provide such a readme after your tests?

Many thanks

Dirk
Fabio Estevam - Dec. 6, 2011, 11:56 a.m.
On Tue, Dec 6, 2011 at 7:41 AM, Dirk Behme <dirk.behme@de.bosch.com> wrote:

> Yes, this is correct. The ~20 line workaround is executed first in the SPI
> NOR and then jumps back to the SD boot routines. Hopefully there will be
> updated/modified boards in the future were the boot mode is configurable,
> again.

Yes, updated boards will allow booting from SD card directly.
...

>
> Fabio: Do you think you could provide such a readme after your tests?

Or maybe we can wait for the new boards to become available.

Let me discuss this option internally.

Regards,

Fabio Estevam

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index 52d86bd..8a4060f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -569,6 +569,7 @@  Jason Liu <r64343@freescale.com>
 	mx53evk         i.MX53
 	mx53loco        i.MX53
 	mx6qarm2	i.MX6Q
+	mx6qsabrelite	i.MX6Q
 
 Enric Balletbo i Serra <eballetbo@iseebcn.com>
 
diff --git a/board/freescale/mx6qsabrelite/Makefile b/board/freescale/mx6qsabrelite/Makefile
new file mode 100644
index 0000000..9b3c493
--- /dev/null
+++ b/board/freescale/mx6qsabrelite/Makefile
@@ -0,0 +1,42 @@ 
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= mx6qsabrelite.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mx6qsabrelite/imximage.cfg b/board/freescale/mx6qsabrelite/imximage.cfg
new file mode 100644
index 0000000..8d3848f
--- /dev/null
+++ b/board/freescale/mx6qsabrelite/imximage.cfg
@@ -0,0 +1,170 @@ 
+# Copyright (C) 2011 Freescale Semiconductor, Inc.
+# Jason Liu <r64343@freescale.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not write to the Free Software
+# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.imxmage for more details about how-to configure
+# and create imximage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+# image version
+
+IMAGE_VERSION 2
+
+# Boot Device : one of
+# spi, sd (the board has no nand neither onenand)
+
+BOOT_FROM	sd
+
+# Device Configuration Data (DCD)
+#
+# Each entry must have the format:
+# Addr-type           Address        Value
+#
+# where:
+#	Addr-type register length (1,2 or 4 bytes)
+#	Address	  absolute address of the register
+#	value	  value to be stored in the register
+DATA 4 0x020e05a8 0x00000030
+DATA 4 0x020e05b0 0x00000030
+DATA 4 0x020e0524 0x00000030
+DATA 4 0x020e051c 0x00000030
+
+DATA 4 0x020e0518 0x00000030
+DATA 4 0x020e050c 0x00000030
+DATA 4 0x020e05b8 0x00000030
+DATA 4 0x020e05c0 0x00000030
+
+DATA 4 0x020e05ac 0x00020030
+DATA 4 0x020e05b4 0x00020030
+DATA 4 0x020e0528 0x00020030
+DATA 4 0x020e0520 0x00020030
+
+DATA 4 0x020e0514 0x00020030
+DATA 4 0x020e0510 0x00020030
+DATA 4 0x020e05bc 0x00020030
+DATA 4 0x020e05c4 0x00020030
+
+DATA 4 0x020e056c 0x00020030
+DATA 4 0x020e0578 0x00020030
+DATA 4 0x020e0588 0x00020030
+DATA 4 0x020e0594 0x00020030
+
+DATA 4 0x020e057c 0x00020030
+DATA 4 0x020e0590 0x00003000
+DATA 4 0x020e0598 0x00003000
+DATA 4 0x020e058c 0x00000000
+
+DATA 4 0x020e059c 0x00003030
+DATA 4 0x020e05a0 0x00003030
+DATA 4 0x020e0784 0x00000030
+DATA 4 0x020e0788 0x00000030
+
+DATA 4 0x020e0794 0x00000030
+DATA 4 0x020e079c 0x00000030
+DATA 4 0x020e07a0 0x00000030
+DATA 4 0x020e07a4 0x00000030
+
+DATA 4 0x020e07a8 0x00000030
+DATA 4 0x020e0748 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e0750 0x00020000
+
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0798 0x000C0000
+
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+
+DATA 4 0x021b0018 0x00081740
+
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b000c 0x555A7975
+DATA 4 0x021b0010 0xFF538E64
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b002c 0x000026D2
+
+DATA 4 0x021b0030 0x005B0E21
+DATA 4 0x021b0008 0x09444040
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0040 0x00000027
+DATA 4 0x021b0000 0x831A0000
+
+DATA 4 0x021b001c 0x04088032
+DATA 4 0x021b001c 0x0408803A
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x0000803B
+DATA 4 0x021b001c 0x00428031
+DATA 4 0x021b001c 0x00428039
+DATA 4 0x021b001c 0x09408030
+DATA 4 0x021b001c 0x09408038
+
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b001c 0x04008048
+DATA 4 0x021b0800 0xA1380003
+DATA 4 0x021b4800 0xA1380003
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00022227
+DATA 4 0x021b4818 0x00022227
+
+DATA 4 0x021b083c 0x434B0350
+DATA 4 0x021b0840 0x034C0359
+DATA 4 0x021b483c 0x434B0350
+DATA 4 0x021b4840 0x03650348
+DATA 4 0x021b0848 0x4436383B
+DATA 4 0x021b4848 0x39393341
+DATA 4 0x021b0850 0x35373933
+DATA 4 0x021b4850 0x48254A36
+
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+
+DATA 4 0x021b480c 0x00440044
+DATA 4 0x021b4810 0x00440044
+
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+
+DATA 4 0x021b001c 0x00000000
+DATA 4 0x021b0404 0x00011006
+
+# set the default clock gate to save power
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC00
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FC
+
+# enable AXI cache for VDOA/VPU/IPU
+DATA 4 0x020e0010 0xF00000FF
+# set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
new file mode 100644
index 0000000..783b0e9
--- /dev/null
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -0,0 +1,150 @@ 
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx6x_pins.h>
+#include <asm/arch/iomux-v3.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+	return 0;
+}
+
+iomux_v3_cfg_t uart2_pads[] = {
+	MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t usdhc3_pads[] = {
+	MX6Q_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6Q_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6Q_PAD_SD3_DAT5__GPIO_7_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t usdhc4_pads[] = {
+	MX6Q_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6Q_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6Q_PAD_NANDF_D6__GPIO_2_6    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+static void setup_iomux_uart(void)
+{
+	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC3_BASE_ADDR, 1},
+	{USDHC4_BASE_ADDR, 1},
+};
+
+int board_mmc_getcd(u8 *cd, struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+
+	if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
+		gpio_direction_input(192); /*GPIO7_0*/
+		*cd = gpio_get_value(192);
+	} else {
+		gpio_direction_input(38); /*GPIO2_6*/
+		*cd = gpio_get_value(38);
+	}
+
+	return 0;
+}
+
+int board_mmc_init(bd_t *bis)
+{
+	s32 status = 0;
+	u32 index = 0;
+
+	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
+		switch (index) {
+		case 0:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+			break;
+		case 1:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) then supported by the board (%d)\n",
+				index + 1, CONFIG_SYS_FSL_USDHC_NUM);
+			return status;
+		}
+
+		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
+	}
+
+	return status;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	puts("Board: MX6Q-Sabre Lite\n");
+
+	return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index f50ec57..cd6585f 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -178,6 +178,7 @@  mx53loco                     arm         armv7       mx53loco            freesca
 mx53smd                      arm         armv7       mx53smd             freescale      mx5		mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg
 vision2                      arm         armv7       vision2             ttcontrol      mx5		vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg
 mx6qarm2                     arm         armv7       mx6qarm2            freescale      mx6		mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg
+mx6qsabrelite                arm         armv7       mx6qsabrelite       freescale      mx6		mx6qsabrelite:IMX_CONFIG=board/freescale/mx6qsabrelite/imximage.cfg
 cm_t35                       arm         armv7       cm_t35              -              omap3
 omap3_overo                  arm         armv7       overo               -              omap3
 omap3_pandora                arm         armv7       pandora             -              omap3
diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h
new file mode 100644
index 0000000..ec9c94b
--- /dev/null
+++ b/include/configs/mx6qsabrelite.h
@@ -0,0 +1,158 @@ 
+/*
+ * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6Q Sabre Lite board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MX6Q
+#define CONFIG_SYS_MX6_HCLK		24000000
+#define CONFIG_SYS_MX6_CLK32		32768
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+#define CONFIG_MXC_UART_BASE		UART2_BASE
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#define CONFIG_BOOTDELAY		3
+
+#define CONFIG_LOADADDR			0x10800000
+#define CONFIG_SYS_TEXT_BASE		0x17800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"uimage=uImage\0" \
+	"console=ttymxc3\0" \
+	"mmcdev=1\0" \
+	"mmcpart=2\0" \
+	"mmcroot=/dev/mmcblk0p3 rootwait rw\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"dhcp ${uimage}; bootm\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev};" \
+	"if mmc rescan ${mmcdev}; then " \
+		"if run loaduimage; then " \
+			"run mmcboot; " \
+		"else run netboot; " \
+		"fi; " \
+	"else run netboot; fi"
+
+#define CONFIG_ARP_TIMEOUT	200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		"MX6QSABRELITE U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE		256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START	0x10000000
+#define CONFIG_SYS_MEMTEST_END		0x10010000
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_STACKSIZE		(128 * 1024)
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM			MMDC0_ARB_BASE_ADDR
+#define PHYS_SDRAM_SIZE			(1u * 1024 * 1024 * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
+#define CONFIG_ENV_SIZE			(8 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		1
+
+#define CONFIG_OF_LIBFDT
+
+#endif				/* __CONFIG_H */