From patchwork Wed Nov 30 16:01:12 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Guo X-Patchwork-Id: 128532 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8346FB6F70 for ; Thu, 1 Dec 2011 02:57:11 +1100 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1RVmU8-0001eN-To; Wed, 30 Nov 2011 15:54:12 +0000 Received: from mail-yx0-f177.google.com ([209.85.213.177]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1RVmU5-0001e9-6a for linux-arm-kernel@lists.infradead.org; Wed, 30 Nov 2011 15:54:10 +0000 Received: by yenq4 with SMTP id q4so745702yen.36 for ; Wed, 30 Nov 2011 07:54:07 -0800 (PST) Received: by 10.50.88.135 with SMTP id bg7mr3475261igb.11.1322668446812; Wed, 30 Nov 2011 07:54:06 -0800 (PST) Received: from localhost.localdomain ([121.236.241.60]) by mx.google.com with ESMTPS id eb23sm9514920ibb.2.2011.11.30.07.54.00 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 30 Nov 2011 07:54:05 -0800 (PST) From: Shawn Guo To: Russell King Subject: [PATCH] arm/imx6: add restart support for imx6q Date: Thu, 1 Dec 2011 00:01:12 +0800 Message-Id: <1322668872-13011-1-git-send-email-shawn.guo@linaro.org> X-Mailer: git-send-email 1.7.4.1 X-Spam-Note: CRM114 invocation failed X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [209.85.213.177 listed in list.dnswl.org] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Sascha Hauer , Shawn Guo , linux-arm-kernel@lists.infradead.org, Arnd Bergmann X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org The restart support was missed from the initial imx6q submission. The mxc_restart() does not work for imx6q. Instead, this patch adds the restart for imx6q. Signed-off-by: Shawn Guo --- Hi Russell, This patch is to support restart support for imx6q based on your 'reset' branch. Is it possible for you to take this patch through your 'reset' branch? arch/arm/mach-imx/clock-imx6q.c | 2 - arch/arm/mach-imx/mach-imx6q.c | 33 ++++++++++++++++++++++++++++++- arch/arm/mach-imx/src.c | 23 +++++++++++++++++++++ arch/arm/plat-mxc/include/mach/common.h | 1 + 4 files changed, 56 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c index 613a1b9..2234031 100644 --- a/arch/arm/mach-imx/clock-imx6q.c +++ b/arch/arm/mach-imx/clock-imx6q.c @@ -1931,14 +1931,12 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) val |= 0x1 << BP_CLPCR_LPM; val &= ~BM_CLPCR_VSTBY; val &= ~BM_CLPCR_SBYOS; - val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; break; case STOP_POWER_OFF: val |= 0x2 << BP_CLPCR_LPM; val |= 0x3 << BP_CLPCR_STBY_COUNT; val |= BM_CLPCR_VSTBY; val |= BM_CLPCR_SBYOS; - val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; break; default: return -EINVAL; diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index dc8b6e2..54ce8ec 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -10,10 +10,13 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include #include +#include #include #include #include +#include #include #include #include @@ -23,6 +26,34 @@ #include #include +void imx6q_restart(char mode, const char *cmd) +{ + struct device_node *np; + void __iomem *wdog_base; + + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-wdt"); + wdog_base = of_iomap(np, 0); + WARN_ON(!wdog_base); + + imx_src_prepare_restart(); + + /* enable wdog */ + writew_relaxed(1 << 2, wdog_base); + /* write twice to ensure the request will not get ignored */ + writew_relaxed(1 << 2, wdog_base); + + /* wait for reset to assert ... */ + mdelay(500); + + pr_err("Watchdog reset failed to assert reset\n"); + + /* delay to allow the serial port to show the message */ + mdelay(50); + + /* we'll take a jump through zero as a poor second */ + soft_restart(0); +} + static void __init imx6q_init_machine(void) { of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); @@ -81,5 +112,5 @@ DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)") .timer = &imx6q_timer, .init_machine = imx6q_init_machine, .dt_compat = imx6q_dt_compat, - .restart = mxc_restart, + .restart = imx6q_restart, MACHINE_END diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c index 36cacbd..117538c 100644 --- a/arch/arm/mach-imx/src.c +++ b/arch/arm/mach-imx/src.c @@ -18,6 +18,7 @@ #define SRC_SCR 0x000 #define SRC_GPR1 0x020 +#define BP_SRC_SCR_WARM_RESET_ENABLE 0 #define BP_SRC_SCR_CORE1_RST 14 #define BP_SRC_SCR_CORE1_ENABLE 22 @@ -39,11 +40,33 @@ void imx_set_cpu_jump(int cpu, void *jump_addr) src_base + SRC_GPR1 + cpu * 8); } +void imx_src_prepare_restart(void) +{ + u32 val; + + /* clear enable bits of secondary cores */ + val = readl_relaxed(src_base + SRC_SCR); + val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE); + writel_relaxed(val, src_base + SRC_SCR); + + /* clear persistent entry register of primary core */ + writel_relaxed(0, src_base + SRC_GPR1); +} + void __init imx_src_init(void) { struct device_node *np; + u32 val; np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src"); src_base = of_iomap(np, 0); WARN_ON(!src_base); + + /* + * force warm reset sources to generate cold reset + * for a more reliable restart + */ + val = readl_relaxed(src_base + SRC_SCR); + val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE); + writel_relaxed(val, src_base + SRC_SCR); } diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 4ee98d5..5ad0497 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -123,6 +123,7 @@ static inline void imx_smp_prepare(void) {} extern void imx_enable_cpu(int cpu, bool enable); extern void imx_set_cpu_jump(int cpu, void *jump_addr); extern void imx_src_init(void); +extern void imx_src_prepare_restart(void); extern void imx_gpc_init(void); extern void imx_gpc_pre_suspend(void); extern void imx_gpc_post_resume(void);