From patchwork Wed Nov 30 04:26:25 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jett.Zhou" X-Patchwork-Id: 128402 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from mail-pz0-f56.google.com (mail-pz0-f56.google.com [209.85.210.56]) (using TLSv1 with cipher RC4-SHA (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority" (verified OK)) by ozlabs.org (Postfix) with ESMTPS id 0A607B6F7B for ; Wed, 30 Nov 2011 15:27:34 +1100 (EST) Received: by mail-pz0-f56.google.com with SMTP id 6sf27320pzk.11 for ; Tue, 29 Nov 2011 20:27:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlegroups.com; s=beta; h=mime-version:x-beenthere:received-spf:from:to:subject:date :message-id:x-mailer:in-reply-to:references:x-originalarrivaltime :x-original-sender:x-original-authentication-results:reply-to :precedence:mailing-list:list-id:x-google-group-id:list-post :list-help:list-archive:sender:list-subscribe:list-unsubscribe :content-type; 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Received: from MSI-MTA.marvell.com ([65.219.4.132]) by na3sys009aob121.postini.com ([74.125.148.12]) with SMTP ID DSNKTtWwstLNYAVSIW2JykJVYHB/29wYrw0C@postini.com; Tue, 29 Nov 2011 20:27:33 PST Received: from maili.marvell.com ([10.68.76.210]) by MSI-MTA.marvell.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 29 Nov 2011 20:26:55 -0800 Received: from localhost (unknown [10.38.34.140]) by maili.marvell.com (Postfix) with ESMTP id 8B4094E4BC; Tue, 29 Nov 2011 20:26:55 -0800 (PST) From: "Jett.Zhou" To: obert.jarzmik@free.fr, a.zummo@towertech.it, haojian.zhuang@gmail.com, linux-arm-kernel@lists.infradead.org, jtzhou@marvell.com, rtc-linux@googlegroups.com, plagnioj@jcrosoft.come Subject: [rtc-linux] [V3 5/6] ARM: sa1100: clean up of the clock support Date: Wed, 30 Nov 2011 12:26:25 +0800 Message-Id: <1322627186-32345-6-git-send-email-jtzhou@marvell.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1322627186-32345-1-git-send-email-jtzhou@marvell.com> References: <1322627186-32345-1-git-send-email-jtzhou@marvell.com> X-OriginalArrivalTime: 30 Nov 2011 04:26:55.0978 (UTC) FILETIME=[4B07CCA0:01CCAF18] X-Original-Sender: jtzhou@marvell.com X-Original-Authentication-Results: gmr-mx.google.com; spf=temperror (google.com: error in processing during lookup of jtzhou@marvell.com: DNS timeout) smtp.mail=jtzhou@marvell.com Reply-To: rtc-linux@googlegroups.com Precedence: list Mailing-list: list rtc-linux@googlegroups.com; contact rtc-linux+owners@googlegroups.com List-ID: X-Google-Group-Id: 712029733259 List-Post: , List-Help: , List-Archive: Sender: rtc-linux@googlegroups.com List-Subscribe: , List-Unsubscribe: , Signed-off-by: Jett.Zhou --- arch/arm/Kconfig | 2 +- arch/arm/mach-sa1100/clock.c | 91 ++++++++++++++++++++++++++++++----------- 2 files changed, 67 insertions(+), 26 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fe6b052..aabc3a6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -737,7 +737,7 @@ config ARCH_SA1100 select ARCH_HAS_CPUFREQ select CPU_FREQ select GENERIC_CLOCKEVENTS - select HAVE_CLK + select CLKDEV_LOOKUP select HAVE_SCHED_CLOCK select TICK_ONESHOT select ARCH_REQUIRE_GPIOLIB diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c index dab3c63..d6df9f6 100644 --- a/arch/arm/mach-sa1100/clock.c +++ b/arch/arm/mach-sa1100/clock.c @@ -11,17 +11,39 @@ #include #include #include +#include +#include #include -/* - * Very simple clock implementation - we only have one clock to deal with. - */ +struct clkops { + void (*enable)(struct clk *); + void (*disable)(struct clk *); + unsigned long (*getrate)(struct clk *); +}; + struct clk { + const struct clkops *ops; + unsigned long rate; unsigned int enabled; }; -static void clk_gpio27_enable(void) +#define INIT_CLKREG(_clk, _devname, _conname) \ + { \ + .clk = _clk, \ + .dev_id = _devname, \ + .con_id = _conname, \ + } + +#define DEFINE_CLK(_name, _ops, _rate) \ +struct clk clk_##_name = { \ + .ops = _ops, \ + .rate = _rate, \ + } + +static DEFINE_SPINLOCK(clocks_lock); + +static void clk_gpio27_enable(struct clk *clk) { /* * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111: @@ -32,38 +54,22 @@ static void clk_gpio27_enable(void) TUCR = TUCR_3_6864MHz; } -static void clk_gpio27_disable(void) +static void clk_gpio27_disable(struct clk *clk) { TUCR = 0; GPDR &= ~GPIO_32_768kHz; GAFR &= ~GPIO_32_768kHz; } -static struct clk clk_gpio27; - -static DEFINE_SPINLOCK(clocks_lock); - -struct clk *clk_get(struct device *dev, const char *id) -{ - const char *devname = dev_name(dev); - - return strcmp(devname, "sa1111.0") ? ERR_PTR(-ENOENT) : &clk_gpio27; -} -EXPORT_SYMBOL(clk_get); - -void clk_put(struct clk *clk) -{ -} -EXPORT_SYMBOL(clk_put); - int clk_enable(struct clk *clk) { unsigned long flags; spin_lock_irqsave(&clocks_lock, flags); if (clk->enabled++ == 0) - clk_gpio27_enable(); + clk->ops->enable(clk); spin_unlock_irqrestore(&clocks_lock, flags); + return 0; } EXPORT_SYMBOL(clk_enable); @@ -76,13 +82,48 @@ void clk_disable(struct clk *clk) spin_lock_irqsave(&clocks_lock, flags); if (--clk->enabled == 0) - clk_gpio27_disable(); + clk->ops->disable(clk); spin_unlock_irqrestore(&clocks_lock, flags); } EXPORT_SYMBOL(clk_disable); unsigned long clk_get_rate(struct clk *clk) { - return 3686400; + unsigned long rate; + + rate = clk->rate; + if (clk->ops->getrate) + rate = clk->ops->getrate(clk); + + return rate; } EXPORT_SYMBOL(clk_get_rate); + +const struct clkops clk_gpio27_ops = { + .enable = clk_gpio27_enable, + .disable = clk_gpio27_disable, +}; + +static void clk_dummy_enable(struct clk *clk) { } +static void clk_dummy_disable(struct clk *clk) { } + +const struct clkops clk_dummy_ops = { + .enable = clk_dummy_enable, + .disable = clk_dummy_disable, +}; + +static DEFINE_CLK(gpio27, &clk_gpio27_ops, 3686400); +static DEFINE_CLK(dummy, &clk_dummy_ops, 0); + +static struct clk_lookup sa11xx_clkregs[] = { + INIT_CLKREG(&clk_gpio27, "sa1111.0", NULL), + INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL), +}; + +static int __init sa11xx_clk_init(void) +{ + clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs)); + return 0; +} + +postcore_initcall(sa11xx_clk_init);