From patchwork Mon Nov 28 18:12:18 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 128043 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 75AE5B6F65 for ; Tue, 29 Nov 2011 05:13:45 +1100 (EST) Received: (qmail 22506 invoked by alias); 28 Nov 2011 18:13:35 -0000 Received: (qmail 22490 invoked by uid 22791); 28 Nov 2011 18:13:34 -0000 X-SWARE-Spam-Status: No, hits=-2.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from mail-vx0-f175.google.com (HELO mail-vx0-f175.google.com) (209.85.220.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 28 Nov 2011 18:13:07 +0000 Received: by vcbfo13 with SMTP id fo13so2308297vcb.20 for ; Mon, 28 Nov 2011 10:13:06 -0800 (PST) Received: by 10.220.106.201 with SMTP id y9mr5183430vco.167.1322503986357; Mon, 28 Nov 2011 10:13:06 -0800 (PST) Received: from localhost.localdomain ([173.160.232.49]) by mx.google.com with ESMTPS id k4sm49909607vdu.2.2011.11.28.10.13.05 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 28 Nov 2011 10:13:05 -0800 (PST) From: Richard Henderson To: gcc-patches@gcc.gnu.org Cc: ebotcazou@libertysurf.fr, davem@davemloft.net Subject: [PATCH 2/5] sparc: Convert to atomic_load/store. Date: Mon, 28 Nov 2011 10:12:18 -0800 Message-Id: <1322503941-7067-3-git-send-email-rth@redhat.com> In-Reply-To: <1322503941-7067-1-git-send-email-rth@redhat.com> References: <1322503941-7067-1-git-send-email-rth@redhat.com> X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org --- gcc/config/sparc/predicates.md | 5 +++ gcc/config/sparc/sparc.md | 1 + gcc/config/sparc/sync.md | 59 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 65 insertions(+), 0 deletions(-) diff --git a/gcc/config/sparc/predicates.md b/gcc/config/sparc/predicates.md index 047b217..a9207be 100644 --- a/gcc/config/sparc/predicates.md +++ b/gcc/config/sparc/predicates.md @@ -239,6 +239,11 @@ (ior (match_operand 0 "register_operand") (match_operand 0 "const_zero_operand"))) +(define_predicate "register_or_v9_zero_operand" + (ior (match_operand 0 "register_operand") + (and (match_test "TARGET_V9") + (match_operand 0 "const_zero_operand")))) + ;; Return true if OP is either the zero constant, the all-ones ;; constant, or a register. (define_predicate "register_or_zero_or_all_ones_operand" diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md index c059dc5..37ac170 100644 --- a/gcc/config/sparc/sparc.md +++ b/gcc/config/sparc/sparc.md @@ -41,6 +41,7 @@ (UNSPEC_MOVE_GOTDATA 19) (UNSPEC_MEMBAR 20) + (UNSPEC_ATOMIC 21) (UNSPEC_TLSGD 30) (UNSPEC_TLSLDM 31) diff --git a/gcc/config/sparc/sync.md b/gcc/config/sparc/sync.md index e22f516..e2f4596 100644 --- a/gcc/config/sparc/sync.md +++ b/gcc/config/sparc/sync.md @@ -102,6 +102,65 @@ "membar\t%1" [(set_attr "type" "multi")]) +(define_expand "atomic_load" + [(match_operand:I 0 "register_operand" "") + (match_operand:I 1 "memory_operand" "") + (match_operand:SI 2 "const_int_operand" "")] + "" +{ + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + + sparc_emit_membar_for_model (model, 1, 1); + + if (TARGET_ARCH64 || mode != DImode) + emit_move_insn (operands[0], operands[1]); + else + emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); + + sparc_emit_membar_for_model (model, 1, 2); + DONE; +}) + +(define_insn "atomic_loaddi_1" + [(set (match_operand:DI 0 "register_operand" "=U,?*f") + (unspec:DI [(match_operand:DI 1 "memory_operand" "m,m")] + UNSPEC_ATOMIC))] + "!TARGET_ARCH64" + "ldd\t%1, %0" + [(set_attr "type" "load,fpload")]) + +(define_expand "atomic_store" + [(match_operand:I 0 "register_operand" "") + (match_operand:I 1 "memory_operand" "") + (match_operand:SI 2 "const_int_operand" "")] + "" +{ + enum memmodel model = (enum memmodel) INTVAL (operands[2]); + + sparc_emit_membar_for_model (model, 2, 1); + + if (TARGET_ARCH64 || mode != DImode) + emit_move_insn (operands[0], operands[1]); + else + emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); + + sparc_emit_membar_for_model (model, 2, 2); + DONE; +}) + +(define_insn "atomic_storedi_1" + [(set (match_operand:DI 0 "memory_operand" "=m,m,m") + (unspec:DI + [(match_operand:DI 1 "register_or_v9_zero_operand" "J,U,?*f")] + UNSPEC_ATOMIC))] + "!TARGET_ARCH64" + "@ + stx\t%r1, %0 + std\t%1, %0 + std\t%1, %0" + [(set_attr "type" "store,store,fpstore") + (set_attr "cpu_feature" "v9,*,*")]) + ;;;;;;;; (define_expand "sync_compare_and_swap"