From patchwork Mon Nov 28 18:12:17 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 128042 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 0CC53B6F75 for ; Tue, 29 Nov 2011 05:13:30 +1100 (EST) Received: (qmail 21332 invoked by alias); 28 Nov 2011 18:13:25 -0000 Received: (qmail 21300 invoked by uid 22791); 28 Nov 2011 18:13:20 -0000 X-SWARE-Spam-Status: No, hits=-2.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from mail-vx0-f175.google.com (HELO mail-vx0-f175.google.com) (209.85.220.175) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 28 Nov 2011 18:13:05 +0000 Received: by vcbfo13 with SMTP id fo13so2308278vcb.20 for ; Mon, 28 Nov 2011 10:13:05 -0800 (PST) Received: by 10.220.38.69 with SMTP id a5mr794208vce.51.1322503984951; Mon, 28 Nov 2011 10:13:04 -0800 (PST) Received: from localhost.localdomain ([173.160.232.49]) by mx.google.com with ESMTPS id k4sm49909607vdu.2.2011.11.28.10.13.03 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 28 Nov 2011 10:13:04 -0800 (PST) From: Richard Henderson To: gcc-patches@gcc.gnu.org Cc: ebotcazou@libertysurf.fr, davem@davemloft.net Subject: [PATCH 1/5] sparc: Convert to mem_thread_fence. Date: Mon, 28 Nov 2011 10:12:17 -0800 Message-Id: <1322503941-7067-2-git-send-email-rth@redhat.com> In-Reply-To: <1322503941-7067-1-git-send-email-rth@redhat.com> References: <1322503941-7067-1-git-send-email-rth@redhat.com> X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org --- gcc/config/sparc/predicates.md | 4 ++ gcc/config/sparc/sparc-protos.h | 2 + gcc/config/sparc/sparc.c | 47 +++++++++++++++++++++++ gcc/config/sparc/sync.md | 79 ++++++++++++++++++++++++++++++++------- 4 files changed, 118 insertions(+), 14 deletions(-) diff --git a/gcc/config/sparc/predicates.md b/gcc/config/sparc/predicates.md index 4dd734f..047b217 100644 --- a/gcc/config/sparc/predicates.md +++ b/gcc/config/sparc/predicates.md @@ -111,6 +111,10 @@ (define_predicate "const_double_or_vector_operand" (match_code "const_double,const_vector")) +;; Return true if OP is Zero, or if the target is V7. +(define_predicate "zero_or_v7_operand" + (ior (match_test "op == const0_rtx") + (match_test "!TARGET_V8 && !TARGET_V9"))) ;; Predicates for symbolic constants. diff --git a/gcc/config/sparc/sparc-protos.h b/gcc/config/sparc/sparc-protos.h index 10fa5ed..b292024 100644 --- a/gcc/config/sparc/sparc-protos.h +++ b/gcc/config/sparc/sparc-protos.h @@ -113,4 +113,6 @@ unsigned int sparc_regmode_natural_size (enum machine_mode); bool sparc_modes_tieable_p (enum machine_mode, enum machine_mode); #endif /* RTX_CODE */ +extern void sparc_emit_membar_for_model (enum memmodel, int, int); + #endif /* __SPARC_PROTOS_H__ */ diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index b315698..c5c4899 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -10849,6 +10849,53 @@ sparc_mangle_type (const_tree type) } #endif +/* Expand a membar instruction for various use cases. Both the LOAD_STORE + and BEFORE_AFTER arguments of the form X_Y. They are two-bit masks where + bit 0 indicates that X is true, and bit 1 indicates Y is true. */ + +void +sparc_emit_membar_for_model (enum memmodel model, + int load_store, int before_after) +{ + /* Bits for the MEMBAR mmask field. */ + const int LoadLoad = 1; + const int StoreLoad = 2; + const int LoadStore = 4; + const int StoreStore = 8; + + int mm = 0; + + if (before_after & 1) + { + if (model == MEMMODEL_ACQUIRE + || model == MEMMODEL_ACQ_REL + || model == MEMMODEL_SEQ_CST) + { + if (load_store & 1) + mm |= LoadLoad | LoadStore; + if (load_store & 2) + mm |= StoreLoad | StoreStore; + } + } + if (before_after & 2) + { + if (model == MEMMODEL_RELEASE + || model == MEMMODEL_ACQ_REL + || model == MEMMODEL_SEQ_CST) + { + if (load_store & 1) + mm |= LoadLoad | StoreLoad; + if (load_store & 2) + mm |= LoadStore | StoreStore; + } + } + + /* For raw barriers (before+after), always emit a barrier. + This will become a compile-time barrier if needed. */ + if (mm || before_after == 3) + emit_insn (gen_membar (GEN_INT (mm))); +} + /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit compare and swap on the word containing the byte or half-word. */ diff --git a/gcc/config/sparc/sync.md b/gcc/config/sparc/sync.md index a7380ab..e22f516 100644 --- a/gcc/config/sparc/sync.md +++ b/gcc/config/sparc/sync.md @@ -1,5 +1,5 @@ ;; GCC machine description for SPARC synchronization instructions. -;; Copyright (C) 2005, 2007, 2009, 2010 +;; Copyright (C) 2005, 2007, 2009, 2010, 2011 ;; Free Software Foundation, Inc. ;; ;; This file is part of GCC. @@ -23,36 +23,87 @@ (define_mode_iterator I48MODE [SI (DI "TARGET_ARCH64 || TARGET_V8PLUS")]) (define_mode_attr modesuffix [(SI "") (DI "x")]) +(define_expand "mem_thread_fence" + [(match_operand:SI 0 "const_int_operand")] + "TARGET_V8 || TARGET_V9" +{ + enum memmodel model = (enum memmodel) INTVAL (operands[0]); + sparc_emit_membar_for_model (model, 3, 3); + DONE; +}) + (define_expand "memory_barrier" - [(set (match_dup 0) - (unspec:BLK [(match_dup 0)] UNSPEC_MEMBAR))] + [(const_int 0)] + "TARGET_V8 || TARGET_V9" +{ + sparc_emit_membar_for_model (MEMMODEL_SEQ_CST, 3, 3); + DONE; +}) + +(define_expand "membar" + [(set (match_dup 1) + (unspec:BLK [(match_dup 1) + (match_operand:SI 0 "const_int_operand")] + UNSPEC_MEMBAR))] "TARGET_V8 || TARGET_V9" { - operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); - MEM_VOLATILE_P (operands[0]) = 1; + operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); + MEM_VOLATILE_P (operands[1]) = 1; }) -;; In V8, loads are blocking and ordered wrt earlier loads, i.e. every load -;; is virtually followed by a load barrier (membar #LoadStore | #LoadLoad). -;; In PSO, stbar orders the stores (membar #StoreStore). -;; In TSO, ldstub orders the stores wrt subsequent loads (membar #StoreLoad). -;; The combination of the three yields a full memory barrier in all cases. +;; A compiler-only memory barrier. Generic code, when checking for the +;; existance of various named patterns, uses asm("":::"memory") when we +;; don't need an actual instruction. Here, it's easiest to pretend that +;; membar 0 is such a barrier. Further, this gives us a nice hook to +;; ignore all such barriers on Sparc V7. +(define_insn "*membar_empty" + [(set (match_operand:BLK 0 "" "") + (unspec:BLK [(match_dup 0) (match_operand:SI 1 "zero_or_v7_operand")] + UNSPEC_MEMBAR))] + "" + "" + [(set_attr "type" "multi") + (set_attr "length" "0")]) + +;; For V8, STBAR is exactly membar #StoreStore, by definition. +(define_insn "*membar_storestore" + [(set (match_operand:BLK 0 "" "") + (unspec:BLK [(match_dup 0) (const_int 8)] UNSPEC_MEMBAR))] + "TARGET_V8" + "stbar" + [(set_attr "type" "multi")]) + +;; For V8, LDSTUB has the effect of membar #StoreLoad +(define_insn "*membar_storeload" + [(set (match_operand:BLK 0 "" "") + (unspec:BLK [(match_dup 0) (const_int 2)] UNSPEC_MEMBAR))] + "TARGET_V8" + "ldstub\t[%%sp-1], %%g0" + [(set_attr "type" "multi")]) + +;; Put the two together, in combination with the fact that V8 implements PSO +;; as its weakest memory model, means a full barrier. Match all remaining +;; instances of the membar pattern for Sparc V8. (define_insn "*membar_v8" [(set (match_operand:BLK 0 "" "") - (unspec:BLK [(match_dup 0)] UNSPEC_MEMBAR))] + (unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")] + UNSPEC_MEMBAR))] "TARGET_V8" "stbar\n\tldstub\t[%%sp-1], %%g0" [(set_attr "type" "multi") (set_attr "length" "2")]) -;; membar #StoreStore | #LoadStore | #StoreLoad | #LoadLoad +;; For V9, we have the full membar instruction. (define_insn "*membar" [(set (match_operand:BLK 0 "" "") - (unspec:BLK [(match_dup 0)] UNSPEC_MEMBAR))] + (unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")] + UNSPEC_MEMBAR))] "TARGET_V9" - "membar\t15" + "membar\t%1" [(set_attr "type" "multi")]) +;;;;;;;; + (define_expand "sync_compare_and_swap" [(match_operand:I12MODE 0 "register_operand" "") (match_operand:I12MODE 1 "memory_operand" "")