diff --git a/arch/arm/cpu/pxa/cpu.c b/arch/arm/cpu/pxa/cpu.c
index c48b2ef..7727554 100644
--- a/arch/arm/cpu/pxa/cpu.c
+++ b/arch/arm/cpu/pxa/cpu.c
@@ -234,21 +234,21 @@ void pxa_gpio_setup(void)
 	writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
 	writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
 	writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 	writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
 #endif
 
 	writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
 	writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
 	writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 	writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
 #endif
 
 	writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
 	writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
 	writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 	writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
 #endif
 
@@ -258,7 +258,7 @@ void pxa_gpio_setup(void)
 	writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
 	writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
 	writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 	writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
 	writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
 #endif
@@ -270,7 +270,7 @@ void pxa_interrupt_setup(void)
 {
 	writel(0, ICLR);
 	writel(0, ICMR);
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 	writel(0, ICLR2);
 	writel(0, ICMR2);
 #endif
diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
index 6504819..ba0de8f 100644
--- a/arch/arm/cpu/pxa/start.S
+++ b/arch/arm/cpu/pxa/start.S
@@ -39,7 +39,7 @@
 #include <config.h>
 #include <version.h>
 
-#ifdef CONFIG_PXA25X
+#ifdef CONFIG_CPU_PXA25X
 #if ((CONFIG_SYS_INIT_SP_ADDR) != 0xfffff800)
 #error "Init SP address must be set to 0xfffff800 for PXA250"
 #endif
@@ -160,7 +160,7 @@ reset:
 	bl  cpu_init_crit
 #endif
 
-#ifdef	CONFIG_PXA250
+#ifdef	CONFIG_CPU_PXA25X
 	bl	lock_cache_for_stack
 #endif
 
@@ -191,7 +191,7 @@ stack_setup:
 	mov	sp, r4
 
 /* Disable the Dcache RAM lock for stack now */
-#ifdef	CONFIG_PXA250
+#ifdef	CONFIG_CPU_PXA25X
 	bl	cpu_init_crit
 #endif
 
@@ -307,7 +307,7 @@ _dynsym_start_ofs:
  *
  *************************************************************************
  */
-#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_PXA250)
+#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
 cpu_init_crit:
 	/*
 	 * flush v4 I/D caches
@@ -327,7 +327,7 @@ cpu_init_crit:
 	mcr	p15, 0, r0, c1, c0, 0
 
 	mov	pc, lr		/* back to my caller */
-#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_PXA250 */
+#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
 
 #ifndef CONFIG_SPL_BUILD
 /*
@@ -519,7 +519,7 @@ fiq:
  * This is useful on PXA25x and PXA26x in early bootstages, where there is no
  * other possible memory available to hold stack.
  */
-#ifdef CONFIG_PXA250
+#ifdef CONFIG_CPU_PXA25X
 .macro CPWAIT reg
 	mrc	p15, 0, \reg, c2, c0, 0
 	mov	\reg, \reg
@@ -602,4 +602,4 @@ mmutable:
 
 	/* 0xfff00000 : 1:1, cached mapping */
 	.word	(0xfff << 20) | 0x1c1e
-#endif	/* CONFIG_PXA250 */
+#endif	/* CONFIG_CPU_PXA25X */
diff --git a/arch/arm/cpu/pxa/timer.c b/arch/arm/cpu/pxa/timer.c
index 2866745..0ad64dd 100644
--- a/arch/arm/cpu/pxa/timer.c
+++ b/arch/arm/cpu/pxa/timer.c
@@ -35,9 +35,9 @@
 #error: interrupts not implemented yet
 #endif
 
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 #define TIMER_FREQ_HZ 3250000
-#elif defined(CONFIG_PXA250)
+#elif defined(CONFIG_CPU_PXA25X)
 #define TIMER_FREQ_HZ 3686400
 #else
 #error "Timer frequency unknown - please config PXA CPU type"
diff --git a/arch/arm/cpu/pxa/usb.c b/arch/arm/cpu/pxa/usb.c
index 0311d5e..83022e2 100644
--- a/arch/arm/cpu/pxa/usb.c
+++ b/arch/arm/cpu/pxa/usb.c
@@ -24,7 +24,7 @@
 #include <common.h>
 
 #if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
-# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X)
+# if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X)
 
 #include <asm/arch/pxa-regs.h>
 #include <asm/io.h>
@@ -37,7 +37,7 @@ int usb_cpu_init(void)
 	writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA);
 	udelay(100);
 #endif
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_CPU_PXA27X)
 	/* Enable USB host clock. */
 	writel(readl(CKEN) | CKEN10_USBHOST, CKEN);
 #endif
@@ -58,7 +58,7 @@ int usb_cpu_init(void)
 #if defined(CONFIG_CPU_MONAHANS)
 	writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR);
 #endif
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_CPU_PXA27X)
 	writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR);
 #endif
 	writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR);
@@ -78,7 +78,7 @@ int usb_cpu_stop(void)
 #if defined(CONFIG_CPU_MONAHANS)
 	writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR);
 #endif
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_CPU_PXA27X)
 	writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR);
 #endif
 	writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR);
@@ -88,7 +88,7 @@ int usb_cpu_stop(void)
 	writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA);
 	udelay(100);
 #endif
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_CPU_PXA27X)
 	/* Disable USB host clock. */
 	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
 #endif
@@ -101,5 +101,5 @@ int usb_cpu_init_fail(void)
 	return usb_cpu_stop();
 }
 
-# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) */
+# endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_CPU_PXA27X) */
 #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h
index 52c79a9..8527c68 100644
--- a/arch/arm/include/asm/arch-pxa/pxa-regs.h
+++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h
@@ -109,7 +109,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define DCSR13		0x40000034  /* DMA Control / Status Register for Channel 13 */
 #define DCSR14		0x40000038  /* DMA Control / Status Register for Channel 14 */
 #define DCSR15		0x4000003c  /* DMA Control / Status Register for Channel 15 */
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 #define DCSR16		0x40000040  /* DMA Control / Status Register for Channel 16 */
 #define DCSR17		0x40000044  /* DMA Control / Status Register for Channel 17 */
 #define DCSR18		0x40000048  /* DMA Control / Status Register for Channel 18 */
@@ -126,7 +126,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define DCSR29		0x40000074  /* DMA Control / Status Register for Channel 29 */
 #define DCSR30		0x40000078  /* DMA Control / Status Register for Channel 30 */
 #define DCSR31		0x4000007c  /* DMA Control / Status Register for Channel 31 */
-#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
 
 #define DCSR(x)		(0x40000000 | ((x) << 2))
 
@@ -134,7 +134,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define DCSR_NODESC	(1 << 30)	/* No-Descriptor Fetch (read / write) */
 #define DCSR_STOPIRQEN	(1 << 29)	/* Stop Interrupt Enable (read / write) */
 
-#if defined(CONFIG_PXA27X) || defined (CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 #define DCSR_EORIRQEN	(1 << 28)	/* End of Receive Interrupt Enable (R/W) */
 #define DCSR_EORJMPEN	(1 << 27)	/* Jump to next descriptor on EOR */
 #define DCSR_EORSTOPEN	(1 << 26)	/* STOP on an EOR */
@@ -438,7 +438,7 @@ typedef void		(*ExcpHndlr) (void) ;
 /*
  * USB Device Controller
  */
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 
 #define UDCCR		0x40600000	/* UDC Control Register */
 #define UDCCR_UDE	(1 << 0)		/* UDC enable */
@@ -797,9 +797,9 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UDCCSR_WR_MASK		(UDCCSR_DME|UDCCSR_FST)
 #define UDC_BCR_MASK		(0x3ff)
 
-#endif /* CONFIG_PXA27X */
+#endif /* CONFIG_CPU_PXA27X */
 
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 
 /******************************************************************************/
 /*
@@ -870,7 +870,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define UP2OCR_CPVPE	(1<<1)
 #define UP2OCR_CPVEN	(1<<0)
 
-#endif	/* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+#endif	/* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
 
 /******************************************************************************/
 /*
@@ -923,7 +923,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define OWER		0x40A00018  /* OS Timer Watchdog Enable Register */
 #define OIER		0x40A0001C  /* OS Timer Interrupt Enable Register */
 
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 #define OSCR4		0x40A00040  /* OS Timer Counter Register 4 */
 #define OSCR5		0x40A00044  /* OS Timer Counter Register 5 */
 #define OSCR6		0x40A00048  /* OS Timer Counter Register 6 */
@@ -951,7 +951,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define OMCR10		0x40A000D8  /* OS Match Control Register 10 */
 #define OMCR11		0x40A000DC  /* OS Match Control Register 11 */
 
-#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
 
 #define OSSR_M4		(1 << 4)	/* Match status channel 4 */
 #define OSSR_M3		(1 << 3)	/* Match status channel 3 */
@@ -1052,7 +1052,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define CKEN4_SSP3	(1 << 4)  /* SSP3 Unit Clock Enable */
 
 #define CCCR_N_MASK	0x0380		/* Run Mode Frequency to Turbo Mode Frequency Multiplier */
-#if !defined(CONFIG_PXA27X)
+#if !defined(CONFIG_CPU_PXA27X)
 #define CCCR_M_MASK	0x0060		/* Memory Frequency to Run Mode Frequency Multiplier */
 #endif
 #define CCCR_L_MASK	0x001f		/* Crystal Frequency to Memory Frequency Multiplier */
@@ -1071,7 +1071,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define CKEN13_FICP	(1 << 13)	/* FICP Unit Clock Enable */
 #define CKEN12_MMC	(1 << 12)	/* MMC Unit Clock Enable */
 #define CKEN11_USB	(1 << 11)	/* USB Unit Clock Enable */
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_CPU_PXA27X)
 #define CKEN10_USBHOST	(1 << 10)	/* USB Host Unit Clock Enable */
 #define CKEN24_CAMERA	(1 << 24)	/* Camera Unit Clock Enable */
 #endif
@@ -1087,7 +1087,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define OSCC_OON	(1 << 1)	/* 32.768kHz OON (write-once only bit) */
 #define OSCC_OOK	(1 << 0)	/* 32.768kHz OOK (read-only bit) */
 
-#if !defined(CONFIG_PXA27X)
+#if !defined(CONFIG_CPU_PXA27X)
 #define	 CCCR_L09      (0x1F)
 #define	 CCCR_L27      (0x1)
 #define	 CCCR_L32      (0x2)
@@ -1120,7 +1120,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define PWM_PWDUTY1	0x40C00004  /* PWM 1 Duty Cycle Register */
 #define PWM_PERVAL1	0x40C00008  /* PWM 1 Period Control Register */
 
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 #define PWM_CTRL2	0x40B00010  /* PWM 2 Control Register */
 #define PWM_PWDUTY2	0x40B00014  /* PWM 2 Duty Cycle Register */
 #define PWM_PERVAL2	0x40B00018  /* PWM 2 Period Control Register */
@@ -1128,7 +1128,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define PWM_CTRL3	0x40C00010  /* PWM 3 Control Register */
 #define PWM_PWDUTY3	0x40C00014  /* PWM 3 Duty Cycle Register */
 #define PWM_PERVAL3	0x40C00018  /* PWM 3 Period Control Register */
-#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
 
 /*
  * Interrupt Controller
@@ -1140,14 +1140,14 @@ typedef void		(*ExcpHndlr) (void) ;
 #define ICPR		0x40D00010  /* Interrupt Controller Pending Register */
 #define ICCR		0x40D00014  /* Interrupt Controller Control Register */
 
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 #define ICHP		0x40D00018  /* Interrupt Controller Highest Priority Register */
 #define ICIP2		0x40D0009C  /* Interrupt Controller IRQ Pending Register 2 */
 #define ICMR2		0x40D000A0  /* Interrupt Controller Mask Register 2 */
 #define ICLR2		0x40D000A4  /* Interrupt Controller Level Register 2 */
 #define ICFP2		0x40D000A8  /* Interrupt Controller FIQ Pending Register 2 */
 #define ICPR2		0x40D000AC  /* Interrupt Controller Pending Register 2 */
-#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
 
 /******************************************************************************/
 /*
@@ -1188,7 +1188,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define GAFR2_L		0x40E00064  /* GPIO Alternate Function Select Register GPIO<79:64> */
 #define GAFR2_U		0x40E00068  /* GPIO Alternate Function Select Register GPIO 80 */
 
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 #define GPLR3		0x40E00100  /* GPIO Pin-Level Register GPIO<127:96> */
 #define GPDR3		0x40E0010C  /* GPIO Pin Direction Register GPIO<127:96> */
 #define GPSR3		0x40E00118  /* GPIO Pin Output Set Register GPIO<127:96> */
@@ -1198,7 +1198,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define GEDR3		0x40E00148  /* GPIO Edge Detect Status Register GPIO<127:96> */
 #define GAFR3_L		0x40E0006C  /* GPIO Alternate Function Select Register GPIO<111:96> */
 #define GAFR3_U		0x40E00070  /* GPIO Alternate Function Select Register GPIO<127:112> */
-#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */
+#endif /* CONFIG_CPU_PXA27X || CONFIG_CPU_MONAHANS */
 
 #ifdef CONFIG_CPU_MONAHANS
 #define GSDR0		0x40E00400 /* Bit-wise Set of GPDR[31:0] */
@@ -1244,7 +1244,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define _GEDR(x)	(0x40E00048 + (((x) & 0x60) >> 3))
 #define _GAFR(x)	(0x40E00054 + (((x) & 0x70) >> 2))
 
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 #define GPLR(x)		(((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3))
 #define GPDR(x)		(((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3))
 #define GPSR(x)		(((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3))
@@ -2123,7 +2123,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define LCCR0_PDD_S	12
 #define LCCR0_BM	(1 << 20)	/* Branch mask */
 #define LCCR0_OUM	(1 << 21)	/* Output FIFO underrun mask */
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_CPU_PXA27X)
 #define LCCR0_LCDT	(1 << 22)	/* LCD Panel Type */
 #define LCCR0_RDSTM	(1 << 23)	/* Read Status Interrupt Mask */
 #define LCCR0_CMDIM	(1 << 24)	/* Command Interrupt Mask */
@@ -2249,7 +2249,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define LCSR1_IU6	(1 << 29)
 
 #define LDCMD_PAL	(1 << 26)	/* instructs DMA to load palette buffer */
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_CPU_PXA27X)
 #define LDCMD_SOFINT	(1 << 22)
 #define LDCMD_EOFINT	(1 << 21)
 #endif
@@ -2480,7 +2480,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define MDREFR_K0RUN	(1 << 13)	/* SDCLK0 Run Control/Status */
 #define MDREFR_E0PIN	(1 << 12)	/* SDCKE0 Level Control/Status */
 
-#if defined(CONFIG_PXA27X)
+#if defined(CONFIG_CPU_PXA27X)
 
 #define ARB_CNTRL	0x48000048  /* Arbiter Control Register */
 
@@ -2494,7 +2494,7 @@ typedef void		(*ExcpHndlr) (void) ;
 #define ARB_CORE_PARK		(1<<24)	   /* Be parked with core when idle */
 #define ARB_LOCK_FLAG		(1<<23)	   /* Only Locking masters gain access to the bus */
 
-#endif /* CONFIG_PXA27X */
+#endif /* CONFIG_CPU_PXA27X */
 
 /* LCD registers */
 #define LCCR4		0x44000010  /* LCD Controller Control Register 4 */
@@ -2628,6 +2628,6 @@ typedef void		(*ExcpHndlr) (void) ;
 #define OSCR4		0x40A00040  /* OS Timer Counter Register */
 #define OMCR4		0x40A000C0  /* */
 
-#endif	/* CONFIG_PXA27X */
+#endif	/* CONFIG_CPU_PXA27X */
 
 #endif	/* _PXA_REGS_H_ */
diff --git a/common/lcd.c b/common/lcd.c
index 6313ec0..bf1a6a9 100644
--- a/common/lcd.c
+++ b/common/lcd.c
@@ -41,7 +41,9 @@
 #include <lcd.h>
 #include <watchdog.h>
 
-#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
+#if defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
+	defined(CONFIG_CPU_MONAHANS)
+#define CONFIG_CPU_PXA
 #include <asm/byteorder.h>
 #endif
 
@@ -512,7 +514,7 @@ void bitmap_plot (int x, int y)
 	uchar *bmap;
 	uchar *fb;
 	ushort *fb16;
-#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
+#if defined(CONFIG_CPU_PXA)
 	struct pxafb_info *fbi = &panel_info.pxa;
 #elif defined(CONFIG_MPC823)
 	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
@@ -528,7 +530,7 @@ void bitmap_plot (int x, int y)
 
 	if (NBITS(panel_info.vl_bpix) < 12) {
 		/* Leave room for default color map */
-#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
+#if defined(CONFIG_CPU_PXA)
 		cmap = (ushort *)fbi->palette;
 #elif defined(CONFIG_MPC823)
 		cmap = (ushort *)&(cp->lcd_cmap[BMP_LOGO_OFFSET*sizeof(ushort)]);
@@ -623,7 +625,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 	unsigned long width, height, byte_width;
 	unsigned long pwidth = panel_info.vl_col;
 	unsigned colors, bpix, bmp_bpix;
-#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
+#if defined(CONFIG_CPU_PXA)
 	struct pxafb_info *fbi = &panel_info.pxa;
 #elif defined(CONFIG_MPC823)
 	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
@@ -663,7 +665,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 #if !defined(CONFIG_MCC200)
 	/* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */
 	if (bmp_bpix == 8) {
-#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
+#if defined(CONFIG_CPU_PXA)
 		cmap = (ushort *)fbi->palette;
 #elif defined(CONFIG_MPC823)
 		cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]);
@@ -752,7 +754,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
 			WATCHDOG_RESET();
 			for (j = 0; j < width; j++) {
 				if (bpix != 16) {
-#if defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS || defined(CONFIG_ATMEL_LCD)
+#if defined(CONFIG_CPU_PXA) || defined(CONFIG_ATMEL_LCD)
 					*(fb++) = *(bmap++);
 #elif defined(CONFIG_MPC823) || defined(CONFIG_MCC200)
 					*(fb++) = 255 - *(bmap++);
diff --git a/drivers/mmc/pxa_mmc.c b/drivers/mmc/pxa_mmc.c
index 3c2905c..2b58a98 100644
--- a/drivers/mmc/pxa_mmc.c
+++ b/drivers/mmc/pxa_mmc.c
@@ -129,7 +129,7 @@ mmc_block_read(uchar * dst, uint32_t src, int len)
 	writel(~MMC_I_MASK_RXFIFO_RD_REQ, MMC_I_MASK);
 	while (len) {
 		if (readl(MMC_I_REG) & MMC_I_REG_RXFIFO_RD_REQ) {
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 			int i;
 			for (i = min(len, 32); i; i--) {
 				*dst++ = readb(MMC_RXFIFO);
@@ -560,7 +560,8 @@ mmc_legacy_init(int verbose)
 	/* Reset device interface type */
 	mmc_dev.if_type = IF_TYPE_UNKNOWN;
 
-#if defined (CONFIG_LUBBOCK) || (defined (CONFIG_GUMSTIX) && !defined(CONFIG_PXA27X))
+#if defined(CONFIG_LUBBOCK) || \
+	(defined(CONFIG_GUMSTIX) && !defined(CONFIG_CPU_PXA27X))
 	set_GPIO_mode(GPIO6_MMCCLK_MD);
 	set_GPIO_mode(GPIO8_MMCCS0_MD);
 #endif
@@ -633,7 +634,7 @@ mmc_legacy_init(int verbose)
 	writel(0, MMC_CLKRT);		/* 20 MHz */
 	resp = mmc_cmd(MMC_CMD_SELECT_CARD, rca, 0, MMC_CMDAT_R1);
 
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#if defined(CONFIG_CPU_PXA27X) || defined(CONFIG_CPU_MONAHANS)
 	if (IF_TYPE_SD == mmc_dev.if_type) {
 		resp = mmc_cmd(MMC_CMD_APP_CMD, rca, 0, MMC_CMDAT_R1);
 		resp = mmc_cmd(SD_CMD_APP_SET_BUS_WIDTH, 0, 2, MMC_CMDAT_R1);
diff --git a/drivers/mmc/pxa_mmc_gen.c b/drivers/mmc/pxa_mmc_gen.c
index 28e37b4..4a7c67a 100644
--- a/drivers/mmc/pxa_mmc_gen.c
+++ b/drivers/mmc/pxa_mmc_gen.c
@@ -30,12 +30,12 @@
 #include <asm/io.h>
 
 /* PXAMMC Generic default config for various CPUs */
-#if defined(CONFIG_PXA250)
+#if defined(CONFIG_CPU_PXA25X)
 #define PXAMMC_FIFO_SIZE	1
 #define PXAMMC_MIN_SPEED	312500
 #define PXAMMC_MAX_SPEED	20000000
 #define PXAMMC_HOST_CAPS	(0)
-#elif defined(CONFIG_PXA27X)
+#elif defined(CONFIG_CPU_PXA27X)
 #define PXAMMC_CRC_SKIP
 #define PXAMMC_FIFO_SIZE	32
 #define PXAMMC_MIN_SPEED	304000
diff --git a/drivers/net/lan91c96.h b/drivers/net/lan91c96.h
index 6fbb0e3..bef1522 100644
--- a/drivers/net/lan91c96.h
+++ b/drivers/net/lan91c96.h
@@ -68,7 +68,7 @@ typedef unsigned long int		dword;
 
 #define	SMC_IO_EXTENT	16
 
-#ifdef CONFIG_PXA250
+#ifdef CONFIG_CPU_PXA25X
 
 #ifdef	CONFIG_LUBBOCK
 #define	SMC_IO_SHIFT	2
@@ -146,7 +146,7 @@ typedef unsigned long int		dword;
 					};  \
 				})
 
-#else /* if not CONFIG_PXA250 */
+#else /* if not CONFIG_CPU_PXA25X */
 
 /*
  * We have only 16 Bit PCMCIA access on Socket 0
diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h
index 895c749..d70c66f 100644
--- a/drivers/net/smc91111.h
+++ b/drivers/net/smc91111.h
@@ -78,7 +78,7 @@ struct smc91111_priv{
 
 #define	SMC_IO_EXTENT	16
 
-#ifdef CONFIG_PXA250
+#ifdef CONFIG_CPU_PXA25X
 
 #ifdef CONFIG_XSENGINE
 #define	SMC_inl(a,r)	(*((volatile dword *)((a)->iobase+((r)<<1))))
@@ -180,7 +180,7 @@ struct smc91111_priv{
 					};  \
 				})
 
-#elif defined(CONFIG_LEON)	/* if not CONFIG_PXA250 */
+#elif defined(CONFIG_LEON)	/* if not CONFIG_CPU_PXA25X */
 
 #define SMC_LEON_SWAP16(_x_) ({ word _x = (_x_); ((_x << 8) | (_x >> 8)); })
 
@@ -249,7 +249,7 @@ struct smc91111_priv{
 					};  \
 				}while(0)
 
-#else				/* if not CONFIG_PXA250 and not CONFIG_LEON */
+#else			/* if not CONFIG_CPU_PXA25X and not CONFIG_LEON */
 
 #ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */
 /*
diff --git a/drivers/serial/serial_pxa.c b/drivers/serial/serial_pxa.c
index 84bb17c..a9976d7 100644
--- a/drivers/serial/serial_pxa.c
+++ b/drivers/serial/serial_pxa.c
@@ -49,7 +49,7 @@ DECLARE_GLOBAL_DATA_PTR;
 #define	BTUART_INDEX	0
 #define	FFUART_INDEX	1
 #define	STUART_INDEX	2
-#elif	CONFIG_PXA250
+#elif	CONFIG_CPU_PXA25X
 #define	UART_CLK_BASE	(1 << 4)	/* HWUART */
 #define	UART_CLK_REG	CKEN
 #define	HWUART_INDEX	0
@@ -68,7 +68,7 @@ DECLARE_GLOBAL_DATA_PTR;
  * Only PXA250 has HWUART, to avoid poluting the code with more macros,
  * artificially introduce this.
  */
-#ifndef	CONFIG_PXA250
+#ifndef	CONFIG_CPU_PXA25X
 #define	HWUART_INDEX	0xff
 #endif
 
diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h
index 14961c1..e449cd7 100644
--- a/drivers/serial/usbtty.h
+++ b/drivers/serial/usbtty.h
@@ -31,7 +31,7 @@
 #include <usb/omap1510_udc.h>
 #elif defined(CONFIG_MUSB_UDC)
 #include <usb/musb_udc.h>
-#elif defined(CONFIG_PXA27X)
+#elif defined(CONFIG_CPU_PXA27X)
 #include <usb/pxa27x_udc.h>
 #elif defined(CONFIG_SPEAR3XX) || defined(CONFIG_SPEAR600)
 #include <usb/spr_udc.h>
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 7d5b504..5e72713 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -37,7 +37,7 @@ COBJS-y += ep0.o
 COBJS-$(CONFIG_OMAP1510) += omap1510_udc.o
 COBJS-$(CONFIG_OMAP1610) += omap1510_udc.o
 COBJS-$(CONFIG_MPC885_FAMILY) += mpc8xx_udc.o
-COBJS-$(CONFIG_PXA27X) += pxa27x_udc.o
+COBJS-$(CONFIG_CPU_PXA27X) += pxa27x_udc.o
 COBJS-$(CONFIG_SPEARUDC) += spr_udc.o
 endif
 endif
diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h
index b604b52..a5ec224 100644
--- a/include/configs/balloon3.h
+++ b/include/configs/balloon3.h
@@ -25,7 +25,7 @@
 /*
  * High Level Board Configuration Options
  */
-#define	CONFIG_PXA27X		1	/* Marvell PXA270 CPU */
+#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
 #define	CONFIG_BALLOON3		1	/* Balloon3 board */
 
 /*
diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h
index 8a3446e..819c5d0 100644
--- a/include/configs/colibri_pxa270.h
+++ b/include/configs/colibri_pxa270.h
@@ -25,7 +25,7 @@
 /*
  * High Level Board Configuration Options
  */
-#define	CONFIG_PXA27X		1	/* Marvell PXA270 CPU */
+#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
 #define	CONFIG_VPAC270		1	/* Toradex Colibri PXA270 board */
 
 #undef	CONFIG_BOARD_LATE_INIT
diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h
index 07bc895..361ffc5 100644
--- a/include/configs/lubbock.h
+++ b/include/configs/lubbock.h
@@ -34,7 +34,7 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_PXA250		1	/* This is an PXA250 CPU    */
+#define CONFIG_CPU_PXA25X		1	/* This is an PXA250 CPU    */
 #define CONFIG_LUBBOCK		1	/* on an LUBBOCK Board	    */
 #define CONFIG_LCD		1
 #ifdef CONFIG_LCD
diff --git a/include/configs/palmld.h b/include/configs/palmld.h
index 514bcaa..88f4bfb 100644
--- a/include/configs/palmld.h
+++ b/include/configs/palmld.h
@@ -25,7 +25,7 @@
 /*
  * High Level Board Configuration Options
  */
-#define	CONFIG_PXA27X		1	/* Marvell PXA270 CPU */
+#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
 #define	CONFIG_PALMLD		1	/* Palm LifeDrive board */
 
 /*
diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h
index 026e183..d1fef25 100644
--- a/include/configs/palmtc.h
+++ b/include/configs/palmtc.h
@@ -27,7 +27,7 @@
 /*
  * High Level Board Configuration Options
  */
-#define	CONFIG_PXA250			1	/* Intel PXA255 CPU */
+#define	CONFIG_CPU_PXA25X			1	/* Intel PXA255 CPU */
 #define	CONFIG_PALMTC			1	/* Palm Tungsten|C board */
 
 /*
diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h
index c208a25..0666f7b 100644
--- a/include/configs/pxa255_idp.h
+++ b/include/configs/pxa255_idp.h
@@ -55,7 +55,7 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_PXA250		1	/* This is an PXA250 CPU    */
+#define CONFIG_CPU_PXA25X		1	/* This is an PXA250 CPU    */
 
 #undef CONFIG_LCD
 #ifdef CONFIG_LCD
diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h
index 2d55044..af464e1 100644
--- a/include/configs/trizepsiv.h
+++ b/include/configs/trizepsiv.h
@@ -40,7 +40,7 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_PXA27X		1	/* This is an PXA27x CPU    */
+#define CONFIG_CPU_PXA27X		1	/* This is an PXA27x CPU    */
 
 #define CONFIG_MMC		1
 #define CONFIG_BOARD_LATE_INIT
diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h
index e78b83a..7802f44 100644
--- a/include/configs/vpac270.h
+++ b/include/configs/vpac270.h
@@ -25,7 +25,7 @@
 /*
  * High Level Board Configuration Options
  */
-#define	CONFIG_PXA27X		1	/* Marvell PXA270 CPU */
+#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
 #define	CONFIG_VPAC270		1	/* Voipac PXA270 board */
 #define	CONFIG_SYS_TEXT_BASE	0xa0000000
 
diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h
index 5c59ac7..941f80c 100644
--- a/include/configs/xaeniax.h
+++ b/include/configs/xaeniax.h
@@ -40,7 +40,7 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_PXA250		1	/* This is an PXA255 CPU    */
+#define CONFIG_CPU_PXA25X		1	/* This is an PXA255 CPU    */
 #define CONFIG_XAENIAX		1	/* on a xaeniax board	    */
 #define	CONFIG_SYS_TEXT_BASE	0x0
 
diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
index 9505007..26204af 100644
--- a/include/configs/zipitz2.h
+++ b/include/configs/zipitz2.h
@@ -25,7 +25,7 @@
 /*
  * High Level Board Configuration Options
  */
-#define	CONFIG_PXA27X		1	/* Marvell PXA270 CPU */
+#define	CONFIG_CPU_PXA27X		1	/* Marvell PXA270 CPU */
 #define	CONFIG_ZIPITZ2		1	/* Zipit Z2 board */
 #define	CONFIG_SYS_TEXT_BASE	0x0
 
diff --git a/include/lcd.h b/include/lcd.h
index 83b50f4..d95feeb 100644
--- a/include/lcd.h
+++ b/include/lcd.h
@@ -87,7 +87,8 @@ typedef struct vidinfo {
 	u_char	vl_wbf;		/* Wait between frames */
 } vidinfo_t;
 
-#elif defined CONFIG_PXA250 || defined CONFIG_PXA27X || defined CONFIG_CPU_MONAHANS
+#elif defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
+	defined CONFIG_CPU_MONAHANS
 /*
  * PXA LCD DMA descriptor
  */
@@ -195,7 +196,7 @@ typedef struct vidinfo {
 	void	*priv;		/* Pointer to driver-specific data */
 } vidinfo_t;
 
-#endif /* CONFIG_MPC823, CONFIG_PXA250 or CONFIG_MCC200 or CONFIG_ATMEL_LCD */
+#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_MCC200, CONFIG_ATMEL_LCD */
 
 extern vidinfo_t panel_info;
 
