From patchwork Sat Nov 26 10:51:34 2011
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Subject: [i386] : Fix sync long long failures on 32bit x86
Date: Sat, 26 Nov 2011 00:51:34 -0000
From: Uros Bizjak <ubizjak@gmail.com>
X-Patchwork-Id: 127777
Message-Id: <CAFULd4YRvkFtRg2x7+Gn=BOi+E_UaunSE5Kvj8B6Eg-eODUGFw@mail.gmail.com>
To: gcc-patches@gcc.gnu.org
Cc: Richard Henderson <rth@redhat.com>, Andrew MacLeod <amacleod@redhat.com>

On Fri, Nov 25, 2011 at 8:31 PM, Uros Bizjak <ubizjak@gmail.com> wrote:

> However, the patch uncovers certain problems with existing fild/fistpl
> implementation of atomic load/store. It fails in several of thread
> simulation tests, i.e.
>
> FAIL: gcc.dg/simulate-thread/atomic-load-longlong.c  -O0 -g  thread
> simulation test
>
> with:
>
> 1: x/i $pc
>
> => 0x8048582 <simulate_thread_main+61>: fild   -0x8(%ebp)
>
> 0x08048585      104           __atomic_store_n (&result, ret, __ATOMIC_SEQ_CST);
>
> 1: x/i $pc
>
> => 0x8048585 <simulate_thread_main+64>: fistp  0x8049ac0
>
> 0x0804858b      104           __atomic_store_n (&result, ret, __ATOMIC_SEQ_CST);
>
> 1: x/i $pc
>
> => 0x804858b <simulate_thread_main+70>: lock orl $0x0,(%esp)
>
> FAIL: Invalid result returned from fetch

At the end of the day, the problem was trivial, missing %Z suffix for
fild and fistp instructions. Attached patch fixes all sync long long
failures, including thread simulation tests.

2011-11-26  Uros Bizjak  <ubizjak@gmail.com>

	* config/i386/sync.md (movdi_via_fpu): Add %Z insn suffixes.

Tested on x86_64-pc-linux-gnu {,-m32} and committed to mainline SVN.

Uros.


Index: sync.md
===================================================================
--- sync.md	(revision 181736)
+++ sync.md	(working copy)
@@ -123,7 +123,7 @@
   DONE;
 })
 
-;; ??? From volume 3 section 7.1.1 Guaranteed Atomic Operations,
+;; ??? From volume 3 section 8.1.1 Guaranteed Atomic Operations,
 ;; Only beginning at Pentium family processors do we get any guarantee of
 ;; atomicity in aligned 64-bit quantities.  Beginning at P6, we get a
 ;; guarantee for 64-bit accesses that do not cross a cacheline boundary.
@@ -281,7 +281,7 @@
 	(unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_MOVA))
    (clobber (match_operand:DF 2 "register_operand" "=f"))]
   "TARGET_80387"
-  "fild\t%1\;fistp\t%0"
+  "fild%Z1\t%1\;fistp%Z0\t%0"
   [(set_attr "type" "multi")
    ;; Worst case based on full sib+offset32 addressing modes
    (set_attr "length" "14")])